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0.18 um technology - what does it mean

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Hope "Channel length" refers to the distance that the charge carrier has to travel btw the drain and source of a Mosfet.
 

As some others already mentioned, 0.35 µm, 0.18 m refer to the minimum DRAWN or in other words "MASK" gate length of the transistor. In reality however, the drain and source regions are n+ diffusion regions for an n-channel transistor and diffuse into the area under the gate, that's why the effective length differs from the drawn length (it is smaller). That means, if you draw the layout of a transistor with a gate length of 0.18 µm, the effective length will be maybe 0.15 µm for example. To my knowledge, the width of the gate cannot be as small as the gate (like a square).
 

0.35 U TECHNOLOGY : THIS MEANS THAT THE MINIMUM CHANNEL LENGTH ( THE LENGHT OF THE POLY OR GATE ) OF THE TRANSISTOR USED IN THE TECHNOLOGY SHOULD BE OF 0.35 U.

THE SAME IS THE CASE WITH THE OTHER TWO TECHNOLOGIES

0.18um : THE MINIMUM CHANNEL LENGTH ( THE POLY OR GATE ) IS 0.18 um
0.90um : THE MINIMUM CHANNEL LENGTH ( THE POLY OR GATE ) IS 0.90 um.

THE 0.35 um TECHNOLOGY IS KNOWN AS " SUB-MICRON TECHNOLOGY "
AND BELOW 0.25 um IS KNOWN AS " DSM - DEEP SUBMICRON TECHNOLOGY"

HOPE THIS SHUD HELP YOU.
 

hi,
Technlogy is nothing but channel width

with regards,
srik.
 

hi,
In cmos technology,transistor is formed by crossing of polysilicon over diffusion. Here 180nm technology refers to polysilicon width only (this is nothing but channel length).
 

some body say that 0.18 is the minimum of half of pitch.
what's half of pitch?
and what's the relationship between half of pitch and channel length?
will u send up a picture to explain these?
thank u :)
 

It's correct!

Normally u use CMOS tech, and the pitch is the space that goes from a ground line to the next one. u have the ground line, the first transistor, vdd line, the second transistor and then the second ground line. In this picture (It's THE STANDARD for the so called "node technology") half pitch is a dimension little greater than the channel lenght. Example 90 nm -> +- .65 nm Leff

bye, ping
 

ping said:
It's correct!

Normally u use CMOS tech, and the pitch is the space that goes from a ground line to the next one. u have the ground line, the first transistor, vdd line, the second transistor and then the second ground line. In this picture (It's THE STANDARD for the so called "node technology") half pitch is a dimension little greater than the channel lenght. Example 90 nm -> +- .65 nm Leff

bye, ping

hi,ping;
will u send up the picture u refer to for us ?
thank u :)
 

well "picture" was metaforical....:)

can I give u some links?

bye, ping
 

It is nothing but width channel of the transistor
 

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