swapna_4a3 said:hi.. this is swapna.. 2009 passout currently doing internship at synopsys hyd from june 15th 2009 to till now..
i have knowledge on vhdl,verilog, system verilog..
I am in search of Front end design..
please tell me if there are any vacancies..
mail id : swapna.lavanuru(at)yahoo.co.in
raghuvlsi said:Respected sir,
I Raghavendra doing MTech in VLSI.Right now iam looking for MTech project.I assure that i definatly useful to your company,please grant me my request.
Skills:verilog HDL,Physical Design using cadance tool,Digital basics.
Thanking you,
Regards,
Raghavendra Rao.V
jagannathkb said:I am Jagannatha KB did my Mtech in VLSI AND MICROELECTRONICS from NATIONAL INSTITUTE OF TECHNOLOGY CALICUT, presently working as Lecturer in BMSIT, Bangalore, I have good understanding and knowledge on digital concepts and have hands on experience of 1 year on industry standard EDA tools (ASIC/FPGA/Design Compiler/Prime Time/ASTRO/Hspice/Microwind2/ SILVACO-Virtual Wafer Fab (ATLAS)/ Xilinx)
RajivKC said:Hii
I have done training in front end VLSI design and verification for 3 months and now I am working a company for 5 months,in Bangalore and am looking for a change.Because,I have done training in system verilog and want to explore more of it,also assertion and functional coverage.I am looking for this kind of work as Verification engineer in ASIC/FPGA.
Please provide me such opportunity and help me learn and explore the new technology.You can mail me at smitianraj2005(at)gmail(dot)com.
Thanks and regards
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