ADC monte carlo simulation

Dear Members,

I did monte carlo simulation of my 3-bit flash ADC. Any suggestion how can I explain the simulation in the text. Like how can I explian my plot in the text. Which factors should I focus on while writing a paragraph about the monte carlo simulation result.

BR

Would be nice if we could see your MC plot. Much easier to help you ;-)

Dear Sir

Attached is my plot. Both are same. One is just background flipped to white. Its for a 3-bit flash ADC with 5 runs in mc.

Regards

musclesinwood said:

Attached is my plot. Both are same. One is just background flipped to white. Its for a 3-bit flash ADC with 5 runs in mc.

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You can't write anything about it if there are no differences to be seen. Which MC libs are included?

Dear Erikl

Here is the monte carlo simulation for both process and mismatch variation for a 3-bit flash ADC. What do you conclude from this plot ?
Library I am using is L130E_HS12_V241_MC_CORNER.lib.scs

regards

What did you change as against the previous simulation?

musclesinwood said:

Here is the monte carlo simulation for both process and mismatch variation for a 3-bit flash ADC. What do you conclude from this plot ?
Library I am using is L130E_HS12_V241_MC_CORNER.lib.scs

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The ADC will not work over corners, process and mismatch variation. It only shows a marginal 2bit resolution with quite different switching voltages.
Try to separate the 3 environment effects. Just start with 3 corner simulations - you don't need MC for this.

Dear erikl

In my previous simulation I did monte carlo simulation of the same circuit for only process variations with 5 runs. This time I did it for both process and mismatch.

As you said in you post

The ADC will not work over corners, process and mismatch variation. It only shows a marginal 2bit resolution with quite different switching voltages.

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What you mean is over the corner simulation , process and mismatch variation , my ADC won't work ?

Try to separate the 3 environment effects. Just start with 3 corner simulations - you don't need MC for this.

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Please explain a little bit what that suppose to mean and how can I do this ?

Really appreciate your help

Regards

the process I m uisng is umc 130nm

musclesinwood said:

What you mean is over the corner simulation , process and mismatch variation , my ADC won't work ?

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Exactly. Only a poor 2bit resolution with quite different switching voltages.

musclesinwood said:

In my previous simulation I did monte carlo simulation of the same circuit for only process variations with 5 runs. This time I did it for both process and mismatch.

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Seems that process variations aren't responsible for the bad behavior.

musclesinwood said:

Please explain a little bit what that suppose to mean and how can I do this ?

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Run 3 or 5 standard simulations with the corner libs (or sections) only: tt, ss, (sf, fs) & ff - and again compare their outputs.

Dear erikl

Alright . I will do the simulation with the corner libs and get back to you with the results. One more thing.
The procedure is same as montecarlo or its different. As in my monte carlo simulation what I did is first I included the model library as mentioned in my previous post on my analog design environment. Then I created a design variable with the value sigma = 3. TheN I clicked the DAC out which is a staircase 3-bit output by selecting outputs to be plotted. Then I chose transient simulation with a time of 2us. After that I clicked on monte carlo on the analog design environment. And did some changes in the mc window like I added process and mismatch variations, number of runs, signals to be plotted.

For the corner simulation as you have mentioned above do I follow the same procedure as mc or there is something different I need to do ?

Thank You
Regards

Dear Erikl

Run 3 or 5 standard simulations with the corner libs (or sections) only: tt, ss, (sf, fs) & ff - and again compare their outputs

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Any tutorial you recommend to do this. And how I choose sigma. Like in my current mc simulation I ma chossing sigma = 3.

And how can I know which model libraries should I include for umc130nm technology for the corner simulation you mentioned above. ?

Regards

musclesinwood said:

For the corner simulation as you have mentioned above do I follow the same procedure as mc or there is something different I need to do ?

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No, run standard simulation setup with the normal libs, no MC libs needed. (I don't know your lib setup).

musclesinwood said:

Any tutorial you recommend to do this.

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Read the Cādence docu. And there are a lot of tutorials to be found in the internet.

musclesinwood said:

And how I choose sigma. Like in my current mc simulation I ma chossing sigma = 3.

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Only necessary for MC simulation. Use sigma=1 (if you don't need millions of chips).

musclesinwood said:

And how can I know which model libraries should I include for umc130nm technology for the corner simulation you mentioned above. ?

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tt for typical, ss for slow, ff for fast process. This is standard nomenclature, but I don't know how UMC calls its libraries resp. sections.

Dear erikl

Attached are the libraries I use which are standard for umc 130nm. Do I need to disable any of the model library while doing the corner simulation ?
So what youre saying is that I should do corner simulation with five different sections, doing corner simulation of each section separately. Like the model library in umc 130nm for section tt ( typical case model ) is L130E_HS_LVT12_V051_MC_CORNER.lib.scs with section: tt. So I should add this library in the model libraries and do corner simulation instead of MC and see results. The disable it and add another section like ss and analyze results ?

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Monte carlo setup plot

musclesinwood said:

Attached are the libraries I use which are standard for umc 130nm. Do I need to disable any of the model library while doing the corner simulation ?

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I think so. But you should find the correct setup in your PDK docu.

musclesinwood said:

So what youre saying is that I should do corner simulation with five different sections, doing corner simulation of each section separately. Like the model library in umc 130nm for section tt ( typical case model ) is L130E_HS_LVT12_V051_MC_CORNER.lib.scs with section: tt. So I should add this library in the model libraries and do corner simulation instead of MC and see results. The disable it and add another section like ss and analyze results

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Right so! Perhaps you can present all 3 (or 5) result curves one below the other, for a simple comparison.

If you want to present information meaningful to a user
the step-points (bit transitions vs voltage) ought to be
Calculator extracted from the results and histogramed
(though 5 iterations is statistically not-useful). These
transition points are your quantity of interest, code vs vin.

You want to understand what is driving the PP+MM
functional falling-apart, twon runs, one with and one
without MM enabled should put that plain. Then you
have to dive in and debug some of the worst ones,
which I think you can do by enabling the same MC
mode and only running the one iteration= variable
value.

It may be useful to add to your testbench, some
NMOS and PMOS devices that are the same geom
and bias as the PCM/WAT tests at the foundry, for
(say) VT and IDsat, anything you can get data for,
so you can criticize the devices as simulated against
the device advertised control ranges. High-sigma
MC simulation may put you far outside WAT limits
and you ought not to be on the hook for the circuit
performance when transistors are "not shippable",
modeling groups will sandbag statistics under direction
from the Methodology Harpies and you have to buck
that, sometimes. On one program way back when
MC was first becoming diktat, I ran the rack of WAT
tests, identified any MCCNT= value which made a
rejectable wafer, and implemented a MC mapping
that skipped unreasonable ones. I sold that story
to the Air Force andtheir tech monitor. But you do
need a solid sense of what's reasonable and
expectable from the fab (which is not the modeling
group) at the bottom of it all, and maybe you don't
get to have that for this exercise.

Dear erikl

Attached are my plots for five different sections. ff, ss, tt, snfp and fnsp. Please have a look and comment. Regards

dick_freebird said:

(though 5 iterations is statistically not-useful).

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In this case it doesn't deal with MC, but with 5 different corner analyses.

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musclesinwood said:

Attached are my plots for five different sections. ff, ss, tt, snfp and fnsp. Please have a look and comment.

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As you can see, the step heights are rather identical, but the 1st step occurs at different time points (I understand that analog input voltage is proportional to time). This suggests an offset and/or gain shift between corners, I'd think.

So, is that correct ? Shall I include this in my report ? And how can I right about it in the report with satisfactory text ?

Regards

musclesinwood said:

... how can I right about it in the report with satisfactory text ?

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Check the stages which could cause offset/gain drifts over temperature and corners. Run INL analyses vs. temperature and corners.

erikl said:

Check the stages which could cause offset/gain drifts over temperature and corners. Run INL analyses vs. temperature and corners.

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Can you please explain a little bit which stages you're talking about as it is a 3-bit flash ADC. And how can I run INL analyses vs. temperature and corners ? I also know how to plot INL/DNL for my ADC.

regards