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[SOLVED] VHDL code for 4-bit-adder using ieee.numeric_std.all

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chopic

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NEED help with VHDL code for 4-bit-adder using ieee.numeric_std.all

Hello =]
I have to write a VHDL code for 4-bit-adder using the ieee.numeric_std.all package.
so i kinda wrote the beggining but my problem is that i dont know how to add to std_logic_vector(s) a single bit of std_logic (carry in ):


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ader is
port (
a,b : in std_logic_vector (3 downto 0) ;
carry_in : in std_logic ;
co : buffer std_logic ;
s : buffer std_logic_vector (3 downto 0) );​
end ader;
architecture arc_ader of ader is
begin
process (a,b,carry_in)
begin

s<= std_logic_vector ( unsigned (a) + unsigned(b) );
.
.
.

how can i add the carry in this way?
please help :-|
 
Last edited:

You can write sth like that:

Code: 
entity test is
	port (
		A : in std_logic_vector (3 downto 0);
		B : in std_logic_vector (3 downto 0);
		C_OUT : out std_logic;
		SUM : out std_logic_vector (3 downto 0)
		);
end entity test;

architecture a_test of test is

begin

	(C_OUT, SUM) <= ('0' & A) + ('0' & B);

end architecture a_test;



---------- Post added at 22:50 ---------- Previous post was at 22:42 ----------

Oh sorry. I havent seen the carry_in isue. Now code would look like:

Code: 
entity test is
	port (
		A : in std_logic_vector (3 downto 0);
		B : in std_logic_vector (3 downto 0);
		C_IN : in std_logic;
		C_OUT : out std_logic;
		SUM : out std_logic_vector (3 downto 0)
		);
end entity test;

architecture a_test of test is

begin
	(C_OUT, SUM) <= ('0' & A) + ('0' & B) + C_IN;
end architecture a_test;


---------- Post added at 22:54 ---------- Previous post was at 22:50 ----------

:D

or prior to VHDL 2k8 you can write sth like that :D :

Code: 
...
	signal C_IN : std_logic;
	signal A,B : std_logic_vector (3 downto 0);
	signal SUM : std_logic_vector (4 downto 0);
begin
	SUM <= ('0' & A) + ('0' & B) + ("" & C_IN);
end architecture;
 
Last edited:
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    chopic

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Tnx but i must use the "unsigned" thing without any concatenation or loops =\
 

Why are your inputs std_logic and std_logic_vector? why not have them as unsigned? then you dont need to do type conversions.

Dave was almost there, but he forgot the unsigned type (or he tried to use the non-standard std_logic_unsigned package). You will have to do some concatenation to get this to work. As another point, I dont like buffer (neither do most people). Standard practice now has most people use internal signals to store values.

But if you insist on using std_logic_vector in ports:

Code: 
architecture arc_ader of ader is
  signal s_i : unsigned(4 downto 0);
begin
  
  s_i <= unsigned ('0' & a) + unsigned('0' & b) + unsigned("0000" & carry_in); 
  
  co <= s_i(4);
  s  <= std_logic_vector(s_i(3 downto 0));

and arc_ader;

No process is needed.
 
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