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modelsim error but activhdl success

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ahmadagha23

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subprogram = ambiguos modelsim

hi,
I tried to compile a vhdl code (from xilinx.com) which contain following line:

"if rst = '1' or std_logic_vector(no_bits_sent) = "1010" then "

by modelsim5.6 i received following error message:

"Subprogram "=" is ambiguous. Suitable definitions exist in package 'std_logic_1164' and 'std_logic_unsigned'."

but activhdl5.1 compiled it successfully. Do you know why and what is the difference between modelsim and activhdl in these situations?


regards
 

ahmadagha23 said:
hi,
I tried to compile a vhdl code (from xilinx.com) which contain following line:

"if rst = '1' or std_logic_vector(no_bits_sent) = "1010" then "

by modelsim5.6 i received following error message:

"Subprogram "=" is ambiguous. Suitable definitions exist in package 'std_logic_1164' and 'std_logic_unsigned'."

but activhdl5.1 compiled it successfully. Do you know why and what is the difference between modelsim and activhdl in these situations?


regards
Click to expand...

The package std_logic_unsigned is NON-STANDARD and hence this situation. Start using numeric_std instead, read VHDL FAQ at www.vhdl.org/comp.lang.vhdl

Regards
Ajeetha, CVC
www.noveldv.com
 

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