Clock Implementation in Verilog

verilog clock buffer

I am doing a project in which im using an always block in which im using
always@(posedge clock)
so where do i implement this clock since im gonna have to synthesize this code and put it on fpga, xc2s200 board, don't know its crystal frequency either. also i need to generate another counter which will count every second and then i need to make some checks based on each second.

If anyone can provide a sample code and i need to implement that in module, i've that clock code for stimulus but i need to implement in my code...

Thanks in advance

global clock verilog

FPGAs do you have built-in clock sources. You have to bring in the clock on an external pin. You declare this as a port pin in the top level of the design and then run it through global clock buffer. The net after the buffer would be labeled "clock" and then synthesizer takes over from there.

The input clock frequency depends on the clock source connected to the FPGA. Some FPGAs have internal PLLs, DLLs, or DCMs that allow you to scale this input frequency up or down within certain limits.

verilog code for clock buffer

Which board do you have? A commercial board probably includes a crystal oscillator with its frequency printed on top. You'll also need to know which FPGA pin connects to the oscillator. Check the board's user manual.

The xc2s200 is a Xilinx Spartan-2. It contains several DLLs as banjo described.

Here's a simple module that inputs a 50 MHz clock, divides it by 50 million, and outputs one pulse per second. You could use the pulse to control other actions. It synthesizes easily in Xilinx XST (part of ISE). XST recognizes the Verilog clock input and automatically inserts the necessary global clock buffer for you.

implementation of verilog

thanks banjo...i get what ur trying to say....
and thanks echo47 the code was very helpful

i really appreciate it

25 mhz clock + verilog

the code is working but i wrote stimulus and changed the value of 50mhz to 2 so that after every two clock edges one sec is generated and in this way im generating 10 secs. but the problem is that it does so after many more clock edges than the 20 im expecting it to be. what's the reason for that?

please give me ur email so i can email u the code

implement two clock edges

The "50 MHz" in line 2 does not affect the counting behavior. It is a Xilinx ISE synthesis timing constraint that tells the synthesizer to route the design so it works reliably up to 50 MHz. You should change this value to your input clock frequency. (This constraint is unnecessary if you have already specified it elsewhere in your ISE project.)

The "50000000" in line 7 controls the counting behavior. You should change this value according to your desired frequency division ratio. For example, if your clock is 2 MHz, and your desired output frequency is 20 Hz, then you should change 50000000 to 2000000/20 (or 100000). It would also be a good idea to change the bit width of the "count" register accordingly.

I don't understand your sentence about two clock edges, 10 seconds, and 20 clock edges. Sorry.

If you need help with your code, it's better to upload it here (perhaps as a ZIP attachment) instead of email, so other people can help you too.