mcfly
Newbie level 5
i wanna know how 2 simulate this vhdl file. i'm currenly using max plus 2 v10.2. i have try to simulate the following fil but i cant get the ouput.
here is the brief about what the vhdl code all about.
there is Length which carries 3 bit. when it see the unique Length bit, it will search for the input denote by DataIn_de3, DataIn_de4, DataIn_de5, DataIn_de6, which can receive 3,4,5, and 6 bit respectively.
Once i put it the stimuli, which is anyof DataIn_de, i cant get the output, denote by DAtaOut_de
i hope some1 can help with this. i hope u guys can simualte it using .vec file or if ther is some correction i need to do in the code
here is the brief about what the vhdl code all about.
there is Length which carries 3 bit. when it see the unique Length bit, it will search for the input denote by DataIn_de3, DataIn_de4, DataIn_de5, DataIn_de6, which can receive 3,4,5, and 6 bit respectively.
Once i put it the stimuli, which is anyof DataIn_de, i cant get the output, denote by DAtaOut_de
i hope some1 can help with this. i hope u guys can simualte it using .vec file or if ther is some correction i need to do in the code