pipelining in verilog

how to bring pipelining in verilog coding of a particular architecture.please give me some example.

The most simplest pipeline is by using latches. Consider a ckt with combinational blocks connected to each other..i.e, the o/p of the 1st block goes as i/p to the next and so on.till it reaches the last o/p stage.. To pipeline this , we simply latch the data between each stage and use a common clock for these latches. This is the simplest pipeline.

In the processor's context, pipelining means to duplicate the basic units, ie, IF,ID,EX unit. If you'r implementing 5 stage pipeline, then u duplicate these blocks 5 times.

What I've said here is just the basics.. there are other considerations to be taken care of when pipelining.

pls elaborate it a bit further...with somecoding examples. i have understood what yu r saying

You can have independent block of code for, say 5 stages of ur processor pipeline......When U give a common clock for all these units and when output of one unit is connected to the following unit...that automatically creates a pipeline..since each unit processing the data from the previous unit in the next clock cycle.

its like a bucket, one fill, next next cascaded

in DC, u mite find some interesting stuff on pipelining...
thr r three commands related to retiming !!
optimize_timing
pipeline_register
register_balance
i hav to luk into doc for correct commands..
u hav separate doc in SOLD for retiming !! go thru it
Shiv

you can find the code in opencore website

Lets say you have a basic 5 stage pipeline IF ID EX MEM WB :

Now, lets say you have two nos. in the instruction which have to be added ADD 05,06 (this is just for the example, one of these HAS to be a register). Now lets look at the clocks :
opcode for ADD = AB (say) so the instruction will look like AB 05 06, lets say we can fetch all three at the same time from the memory

Clock 1 : IF
AB 05 06 are fetched from memory. the data is latched and sent to the second stage of pipeline
sample code:
always @ (posedge sys_clk)
opcode <= AB; (n registers used)
data1 <= 05; (m registers used)
data2 <= 06; (m registers used)


Clock 2 : ID
here we know that the instrn is ADD so we send it to ALU which is the third stage
sample code :

always @ (posedge sys_clk)
ALU_op <= op_code; (decoding takes place here = some combinational logic + n regs)
ALU_data1 <= data1; (m more regs)
ALU_data2 <= data2; (m more regs)

Clock 3 : EX
Here the data is added within the ALU. Now, understand here that the data (05 06) was available in the first stage itself (clock 1)
Inspite of that we had to pass it through the first 2 stages so that the opcode and both data are availbale at the ALU during clock 3.
In other words this data passes through 2 pipeline stages ( = additional flops/registers)

Now, lets say you needed the output of the ALU in stage 5 (maybe a previous instruction needs this). So the data can be sent to stage 5 directly.
No need to pass it through stage 4 & 5. This is known as forwarding in pipeline. For details refer to Computer Architecture : hardware software approach by hennessey and patterson.
This has been explained very well in that book.

Basically each pipeline stage is simply the output of the pervious stage seperated by a flop.

HTH,
B