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What is the exact defination of clock skew related to digital/VLSI system?

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jinal patel

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what is the exact defination of clock skew related to digital /VLSI system?
 

Re: Clock Skew

difference in time between origin of clock and destination of clock where it needs to sample the data
 

Clock Skew

No, that sounds more like propagation delay.

The Xilinx ISE user manual glossary defines "skew" as "The time differential between two or more destination pins in a path".

Wikipedia info:
https://en.wikipedia.org/wiki/Clock_skew
 

Clock Skew

clock skew is the difference in the arrival times of clock at the clock pin of the flops. early arrival can cause set up violation and late arrival can cause hold violation. basically at every next clock there should be transfer from one flop to another flop. that difference value is called as slack accordingly positive n negative............for a design to run correctly there should be positive slack taking care of the margins as well.
 

Re: Clock Skew

Clock skew is normally defined as the time it takes to reach the different flip-flops... If the threr is a long clk path between 2 flops, thr will be more skew... To avoid this kind of prob, we use H-tree connection...
 

Clock Skew

we can use DCM ( digital clock manager ) for CLock-Deskew
 

Re: Clock Skew

clock skew the spatial variations of the arrival of the clock... it is due to delay in the clock path to various flops... it has serious effects on the design...like the setup and hold time violation... it is over come by using various routing techniques...
 

Re: Clock Skew

Due to wire interconnection , there may be delay in clock to arrive at a port , than what expected, .. There r two types of skew.. Positive and negative,, both have severe prob in design
 

Re: Clock Skew

positive skew can improve the performance of your circuit by increasing the clock frequency... howeer the ciruit can become suseptible to race condition...i.e it might result in hold time violation...
 

Re: Clock Skew

To lordsathish,

Can u pl explain in detail, how the positive skew can improve the performance?..
Pl give any link which deals with it..


Regards,
Venkatesan.s
 

Re: Clock Skew

positive skew means that the next clock to the next adjacent shift register to which the data propagates arrives late when compared to the ideal clock... hence we have larger time for the data to propagate through the flip flop and combinational logic and become valid for the next flip flop...
thus this could improve the clock frequency of the circuit....
however if the minimum delay of the circuit is so small that the data propagates and can make a hold time violation at for the same clock in the next flip flop.....
 

Clock Skew

lordsathith:
wouldn't this be of benefit only for the offset in requirement, and be a bad thing on the offset out requirement? seems like a wash, no?
 

Re: Clock Skew

Hey i couldn get your question... the offset can be advantageous as well as a disadvantage depending on the conditions imposed by the circuit....
 

Re: Clock Skew

Consider just two flops connected via a combinational circuit .. if the flop1 responds to the rising edge of the clock cycle then the flop must respond to the next rising edge but due to some interconnect delay it will not respond to rising edge exactly.. this can be positive or negative... both must be taken care as they have their effects in circuits...
 

Re: Clock Skew

Shans60 said:
Consider just two flops connected via a combinational circuit .. if the flop1 responds to the rising edge of the clock cycle then the flop must respond to the next rising edge but due to some interconnect delay it will not respond to rising edge exactly.. this can be positive or negative... both must be taken care as they have their effects in circuits...
Click to expand...

Shans60,
Clock skew is a spatial variation of the clock . but i think u have explained something different.. If the clock is not responding to second clock edge,
do u mean there is change in clock period?????...

Regards,
Venkatesan.s
 

Re: Clock Skew

the clock skew is defined by the arriving time difference between two DFF's clock

edage.

best regards




jinal patel said:
what is the exact defination of clock skew related to digital /VLSI system?
Click to expand...
 

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