sudhirkv
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Hi
I have to design a FIFO where SDRAM is running at 50Mhz and LCD controller is also working at 50Mhz. SDRAM can access a data width of 32 bit and LCD can only access 16 bit. Here SDRAM takes 14 cycles for a burst length of 8 to output data. whereas LCD controller can only access one 16 bit in 7 cycles.
So how much depth should be my FIFO for preventing underlfow or over run.
Thanks in advance
I have to design a FIFO where SDRAM is running at 50Mhz and LCD controller is also working at 50Mhz. SDRAM can access a data width of 32 bit and LCD can only access 16 bit. Here SDRAM takes 14 cycles for a burst length of 8 to output data. whereas LCD controller can only access one 16 bit in 7 cycles.
So how much depth should be my FIFO for preventing underlfow or over run.
Thanks in advance