How to generate differential clock output in Virtex II with single input clock?

hi all,

i want to generate differentiel clock output in virtex two with single input clock
at 100mhz.

what do you think about OBUFDS.

thank s in advance regards

single to diff clock

We used the Xilinx Virtex2 in past projects. I do not think it has a differential output mode. It only natively supports differential inputs.

Here is how we got differential outputs clocks. For the "positive" output terminal, use a the DDR output structure and connect the single-ended clock to both clock inputs to the IOB. Tie the rising edge flops "D" input to "1" and tie the falling edge flops "D" input to "0'.
For the "negative" output terminal, use the DDR output structure and do the opposite. Use the single-ended clock to both clock inputs of the IOB. Tie the rising edge flops "D" input to "0" and tie the falling edge flops "D" input to "1".
Assuming the clock skew between these IOBs is very small which is should be if they are physically close, you get a differential clock output at the same frequency as the single-ended internal clock.

We did this with structural Verilog and just instantiated the IOB structures directly. You can get the names of the elements for your particular family from the user's guide.