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Cell delay is the amount of delay from input to output of a logic gate
in a path. The values of cell delay can be got from Timing libraries (i.e., .lib )
or from SDF files if they are available.
Net delay is the amount of delay from the output of a cell to the input
of the next cell in a timing path. Net delay is due to parasitic resistance and capacitence of net connection between cells .The significance of this is it may limit the Drive strength of net.
Net delays can be caluculated from SDF,DSPF,RSPF.
or can be estimated from Wire Load Models available in .lib file.
Cell delay is the amount of delay from input to output of a logic gate
in a path. The values of cell delay can be got from Timing libraries (i.e., .lib )
or from SDF files if they are available.
Net delay is the amount of delay from the output of a cell to the input
of the next cell in a timing path. Net delay is due to parasitic resistance and capacitence of net connection between cells .The significance of this is it may limit the Drive strength of net.
Net delays can be caluculated from SDF,DSPF,RSPF.
or can be estimated from Wire Load Models available in .lib file.
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