indomitable12345
Member level 1
i have xilinx ise webpack in which i could synopsys library for arithmetic functions in vhdl but not for verilog.why is it so??..are the arithmetic functions very useful,i mean do they generate a high speed and highly optimised arithmetic functions,because i have started writing the dut in verilog,but,if i have to use the library,then i will have to code it in vhdl....