wjccentury
Junior Member level 2
gate dft mix_clocks
When I insert scan chain in a module (not big, only 8 chains).
I found many scan flip-flops missing in the chain. The scan check report says:
Shift clock pin CK of cell ××_reg is illegally gated.(TEST-186)
My test clock is TCLK, only one. The missing scan flip-flops are all clocked by the gate clock from the clock_gating_cell.
TCLK------>combinational clock_gating_cell------>scan flip-flip
Synopsys sold says "DFT compilier supports combinational clock gating during the parallel capture cycle"
My scan configuration is:
full_scan, multiplexed_flip_flop, mix_clocks, -internal_clocks(false), -replace(ture), -disable(true), -add_lockup(false)
Who can tell me why? Thank you very much !
When I insert scan chain in a module (not big, only 8 chains).
I found many scan flip-flops missing in the chain. The scan check report says:
Shift clock pin CK of cell ××_reg is illegally gated.(TEST-186)
My test clock is TCLK, only one. The missing scan flip-flops are all clocked by the gate clock from the clock_gating_cell.
TCLK------>combinational clock_gating_cell------>scan flip-flip
Synopsys sold says "DFT compilier supports combinational clock gating during the parallel capture cycle"
My scan configuration is:
full_scan, multiplexed_flip_flop, mix_clocks, -internal_clocks(false), -replace(ture), -disable(true), -add_lockup(false)
Who can tell me why? Thank you very much !
