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verilog error - ise 9.1i XST sysnthesize error need help

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kalpana.aravind

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verilog multi-source error 528

Hi All,

I have installed ISE 9.1i free webpack. and running ise 7 tutorial which I downloaded from xilinx website.
while doing synthesize using XST synthesizer, I am getting following error, how to solve the error. Please If any of u have run free tutorial on ise please help me to solve this.

ERROR : Xst:528 - Multi-source in Unit <stopwatch> on signal <hex2led_int1<0>>
Sources are:
Dangling signal <HEX2LED_1/HEX<0>> in Unit <hex2led> is tied to 0 by XST
Output signal of FDCE instance <TENCNT_1/BU2/U0/q_i_0>

any suggestions welcome. waiting for reply.
thanks in advance
 

is tied to 0 by xst

hex2led_int1<0> may have a multiple driver.
if u can post the code someone ere may help u
 

dangling signal multisource xst

"WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."

This warning often appears in conjunction with "Xst:529."

Solution 1:

This warning appears when XST determines that there is contention on a particular signal. If the processes assigning values to this signal are mutually exclusive (as in the case of 3-state buffers), this message can be ignored.

However, in most cases, XST is able to determine when multiple drivers are illegal, and will stop synthesis soon after this message.

Check this signal and modify your code to avoid the existing contention.
Solution 2:

In some cases, XST ties unconnected output ports to ground. If the output port is part of a 3-state bus, which in turn connects to another 3-state bus, then connecting one bit of the bus to ground will cause a multiple-driver error. Verify that this is not occurring in your design by searching for the following warning:

"WARNING:Xst:1305 - Output <dataout<23>> is never assigned. Tied to value 0."

To work around this issue, remove the unused output port.
Solution 3:

This has also been seen in the following condition:

When there is an association signal named to_qvm_d4.Q_num.

When using association signal(to_qvm_d4.Q_num), XST will rename it to "to_qvm_d4_Q_num" during synthesis. There is signal named "to_qvm_d4_Q_num" in the same architecture. XST is confused with these two signals and errors.

To work around this issue, rename either of the two signals.
 

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