Bus Functionality Model..........What is this

Hi everyone........

can anyone explain in brief Bus Functionality Model


Thanks

"An intelligent BFM provides a transaction-level API, and is designed to handle concurrency and parallelism. This makes it suitable to be used in an automated test generation environment. It provides a consistent programmer''s view. It also offers a high degree of controllability for the model behavior to emulate a real device with real operating characteristics through programmable delay registers and configuration registers."

this is the explanation i found in "verification methodology manual".

in other words, its just a program, which provides an interface to the user, taking simple inputs from her/him to generate the data required by the DUT.

correct me if i'm wrong, a simple example would be a parallel-to-serial converter, which provides data to the serial input interface of the dut by taking parallel data from the user.

BFM is simple model for complex IP core, such as cpu core, you can use BFM to test system interconnections instead of real CPU core model, because BFM is much faster than core model. another merit of BFM is easy test stimulus generation, for BFM provide transaction level routine, can be called by test case, to form master bus transfer sequence.
BFM is very popular in bus-based Soc and Communication type ASIC design.