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Help me design divide by 3 ckt with 50% duty cycle

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rajakash

rajakash

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design divide by 3 ckt with 50% duty cycle.(hind double the clk)

hi friends, can anyone tell the clue for doing this problem ......................
 

Re: clock divider

Below are circuits that divides input clock by 3 (with 50% duty cycle) but without multiplying input signal ..

Regards,
IanP
 

setup time and hold time

wat is mean by duty cycle.............. and wat is mean by 50% of duty cycle ....can u give the answer pls

Added after 1 hours 59 minutes:

wat is setup and hold time violation ?
 

Re: clock divider

Duty Cycle = Ton/T.............

50% duty cycle refers to
Time of Ton = Time of Toff
 

Re: setup time and hold time

rajakash said:
wat is mean by duty cycle.............. and wat is mean by 50% of duty cycle ....can u give the answer pls

Added after 1 hours 59 minutes:

wat is setup and hold time violation ?
Click to expand...

violation means that u don't respect the minimum requirements of these time constraints, and your circuit won't function correct
 

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