question of comparator

Here is an open-loop comparator .

It is said that the M8--M11 added to provide drive capability and minimize propagation delay.

But I don't know why, can someone explain this?

thanks

Regards

I think Phillip E.Allen's 'CMOS Analog Circuit Design' section 8.3 - Other Open-loop Comparators can help you

Each inverter is actually a gain stage. Properly sized inverter chain is used to pull the comparator output to the positive or negative supply voltage level with little delay. But if the gain of the input stage is not adequate enough, large short circuit current will occur through the first one or two inverters.

these tran. just work as inverter.so it's buffers.

The M8-M11 is properlly sized . If the size of M10 , M11 is e times of M8,M9 ,
the delay time is minimized .
In fact , M8-M11 compose of a buffer to drive the Cout .This tech is widely used
in digitlal circuit.

M8-M11 give two-stage comparator's output a certian small capacitor,if non this
buffer,maybe there is a large cap,then capability become worse & propagation delay become longer.

could someone tell me how to size the inverter chain? theoreticall,it's "e". however, in practice, some circuits use "4 times", others uses "3 times".

could someone explain it??
thanks!

this technique is widely used in digital logics where you need to drive large cap loads.

instead of making one large inverter(it offers large capacitance to the previous driver )which starts slowly ,they make small inverters(scaled in G.P) to drive the cap. to reduce the time delay.

u can prove that the scaling shd be in G.P to get least delay. ratio will be approx. 2.71
considering the time delay of inverter.

Hi,
M6-M7 driving capability is limited by BIAS,
that's why we need buffer to drive output load.

the output inverters converts the swing from few milli volts to rail to rail ie 0 to vsupply,if you need to get the inverted output you can use one inverter else non inverting means two inverters,these inverters are designed carefully it should not add any delay to the signal and also to load the output capacitance normally 1pf or depends on the specification

One thing folks, any active circuit in the path will add to delay. But I will try to sum up things as said earlier.

1. But what needs to be really looked into is the propagation delay, which is the delay for charging or discharging a capacitive load.

2. The M5 and M6 are definately limited by the bias current. Hence the cap load needs buffering. The buffer implemented as an inverter chain, are actually current unlimited amplifiers(Class B).

3. The inverter chain is not for giving gain. I am sure that the initial stage provides enough gain for the signal. The inverter chain ensures that the swing is rail to rail.

4. The sizing of the inverters starts with the last inverter. Put a cap load you want to drive. Size the inverter W/Ls so that there is minimum propagation delay. Now look into the gate capacitance of the last inverter. Size the preceeding inverter to drive this gate capacitance.

I hope that you got the point

I agree with Vamsi Mocherla. Good illustration.

liuyonggen_1 said:

could someone tell me how to size the inverter chain? theoreticall,it's "e". however, in practice, some circuits use "4 times", others uses "3 times".

could someone explain it??
thanks!

Click to expand...

to get the min. delay, for fixed taper factor inverter chain, the scale factor of inverter is e, 2.718, so, people sometimes use 3, also, 3 or 4 are similar reason, and factor 4=2^2 is easy to calculate. also, using factor 4 can save one or two stages if the driver chain is long, in that case, power consumption can also be saved a little bit.

A faster comparator should ba a pre amplifier (gain of 4-6) followed by a latch.