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Converting real values to stdlogic for VHDL code

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vinodkumar

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hi
iam implementing an algorithm in which my inputs are real values.what i know is real ports r not synthesizable.what i thought of is to convert to stdlogic and then implement.for this i need a package.right.if this is correct and anybody already worked on converting from real to stdlogic plz help me i will be vary much thankful.
if my thought is wrong.plz suggestd other esier methods.
 

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