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how to go Binary addition in vhdl with vectors

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s3034585

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vhdl addition

Hi Guys

Can anyone pls tell me how to do binary addition with vectors...
i tried to do but it gives me a error as "Type error resolving infix expression "+" as type std_logic_vector."
Code VHDL - [expand]
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Library IEEE;
Use Ieee.std_logic_1164.all;
 
  entity add is
  Port(   
      a: in std_logic_vector(3 downto 0)  ;
       sum:out std_logic_vector(3 downto 0)
      );
  end add;
 
  architecture behav of add is
      signal tmp : std_logic_vector(3 downto 0);
 begin
     
 
    tmp <= a(0) + a(1) +a(2) + a(3) when en = '1' else "0000";
    sum <= tmp;
 
end behav;
 
Last edited by a moderator:

addition in vhdl

Hi!
Just add:
1. Use Ieee.std_logic_unsigned.all;
2. en: in std_logic;
3. you have to extend a(0), a(1) etc to 4bit by "000"&

Have a nice day!


Code: 
Library IEEE; 
Use Ieee.std_logic_1164.all; 
Use Ieee.std_logic_unsigned.all; 

entity add is 
Port( 
a: in std_logic_vector(3 downto 0) ; 
en: in std_logic;
sum:out std_logic_vector(3 downto 0) 
); 
end add; 

architecture behav of add is 
signal tmp : std_logic_vector(3 downto 0); 
begin 


tmp <= (("000"&a(0)) + ("000"&a(1))+ ("000"&a(2)) + ("000"&a(3))) when en = '1' else "0000"; 
sum <= tmp; 

end behav;
[/code]
 

vhdl std_logic_vector addition

dunets said:
Hi!
Just add:
1. Use Ieee.std_logic_unsigned.all;
2. en: in std_logic;
3. you have to extend a(0), a(1) etc to 4bit by "000"&

Have a nice day!


Code: 
Library IEEE; 
Use Ieee.std_logic_1164.all; 
Use Ieee.std_logic_unsigned.all; 

entity add is 
Port( 
a: in std_logic_vector(3 downto 0) ; 
en: in std_logic;
sum:out std_logic_vector(3 downto 0) 
); 
end add; 

architecture behav of add is 
signal tmp : std_logic_vector(3 downto 0); 
begin 


tmp <= (("000"&a(0)) + ("000"&a(1))+ ("000"&a(2)) + ("000"&a(3))) when en = '1' else "0000"; 
sum <= tmp; 

end behav;
[/code]
Click to expand...

Hi Dunets
Thanks a lot for your help.
tama
 

vhdl binary addition

s3034585 said:
Hi Guys

Can anyone pls tell me how to do binary addition with vectors...
i tried to do but it gives me a error as "Type error resolving infix expression "+" as type std_logic_vector."

Library IEEE;
Use Ieee.std_logic_1164.all;

entity add is
Port(
a: in std_logic_vector(3 downto 0) ;
sum:eek:ut std_logic_vector(3 downto 0)
);
end add;

architecture behav of add is
signal tmp : std_logic_vector(3 downto 0);
begin


tmp <= a(0) + a(1) +a(2) + a(3) when en = '1' else "0000";
sum <= tmp;

end behav;
Click to expand...


include the foolowing libraries
arith and unsigned too then they will executed
 

addition vhdl

i prefer the numeric lib instead of arth lib, the latter is synopsys prepoerity.
 

can someone please explain to me what this does ("0000"&a(0)) in this particular line of text below. the exact code is in one of the replies on this thread

Code: 
tmp <= (("000"&a(0)) + ("000"&a(1))+ ("000"&a(2)) + ("000"&a(3))) when en = '1' else "0000"; 
sum <= tmp;
 

It creates a vector. a(0) is a single bit. Only vectors of type signed or unsigned can be added together.
 

The code calculates the number of '1' bits in input vector a. Is this what you want to achieve?

The question title might suggest that you want to add multiple vectors. But there's only one input vector.
 

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