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VERILOG RTL code for PRBS generator

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kma

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prbs generator

Can anyone tell me how to get the VERILOG RTL code for PRBS generator? Thanks.
 

prbs verilog

Here are the key lines of code for a 19-bit LFSR, which generates a PRBS. The output is simply lfsr bit 0.

Code:
  reg [18:0] lfsr=0;

  always @ (posedge clock)
    lfsr <= {lfsr, ~lfsr[18]^lfsr[5]^lfsr[1]^lfsr[0]};
If you need a different cycle length, try this Xilinx app note:
https://www.xilinx.com/bvdocs/appnotes/xapp210.pdf
 

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