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Pulse width modulation

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ei99dami

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Hi,

Is it possible to create a 10 MHz pulse width modulated signal from a FPGA?

/Robin
 

Of course. What FPGA are you using?
 

The FPGA is a Altera Stratix II or Virtex 4.
The resolution for the 10 MHz signal is 2^8. (clk in to FPGA will be 2550 MHz)
That will be a problem.

/Robin
 

you can use the PLL in the FPGA to reduce the CLK. and then use logic do set your pulse pattern
 

Can you please evolve what you mean with the PLL and how to implement the logic and set up your pulse pattern.

/Robin
 

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