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library ieee;
use ieee.std_logic_1164.all;
entity dig_ff is
port(
d : in std_logic_vector (15 downto 0); -- input data
clk ,rst : in std_logic; -- clock and rest
q : out std_logic_vector (15 downto 0));--output data
end dig_ff;
architecture cct of dig_ff is
begin
process(rst, clk)
begin
if (rst = '0') then --asynch reset
q <= (others=>'0');
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end cct;
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