Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

VERILOG :if-else generate statement

Status
Not open for further replies.
C

choonlle

Full Member level 2
Joined
Jul 18, 2006
Messages
126
Helped
20
Reputation
40
Reaction score
1
Trophy points
1,298
Location
AFRICA
Activity points
2,025
Hi,
The purpose of generate statement is used to provide a far more powerful capability to create multiple instances of an object.
But,
For below case, what is the diff between case 1 and case 2 ? the cases do not create multiple instances of an object, so what is the different?

Case 1:
generate
if (status) begin
pipe_line(.dout(dout),
.din(din),
.clk(clk))
end
else
begin
assign dout=reg[15:0]
end
end generate

Case 2
if (status) begin
pipe_line(.dout(dout),
.din(din),
.clk(clk))
end
else
begin
assign dout=reg[15:0]
end

Please let's me know the advantage of above case wif using generate statement!


Thanks!!!!!
 

Your second case is illegal Verilog - regular if..else is a procedural construct and hence can't be used in concurrent portion. Did your code compile?

Regards
Ajeetha, CVC
www.noveldv.com
 

hi,

if the case 1 is correct, what is the advantage of using generate statement if compare to the generate statement,where it can generate multiple instance of instantiation?

Beside, if we try to generate statement, any feature beside multiple instantiate the block??


Hope to hear from you soon.


thanks a lot...
regards,
choonlle
 

Hi,
Generate can be used for several things:

1. Multiple instantiations of a same module
2. Optional choice of which module to choose - say gate level vs. RTL or RTL vs. behaviora letc.

generate..if is used to satisy #2 above. In your example, depending on the value of "status" at elaboration time you will get pipe_line module instantiation or simply the assign statement.

Read:

http://www.sunburst-design.com/papers/CummingsDVCON2003_V2K1_SimScore.pdf

for more

HTH
Ajeetha, CVC
www.noveldv.com
 

    C

    choonlle

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top