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How to detect High-Z state in VHDL

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hi

How to detect High-Z state in VHDL

like some ICS,can be set 3 kind of working mode by 1 input pin

ex: input pin='HI' ->mode1
input pin='LO' ->mode2
input pin='High-Z' ->mode3

thank you
 

High impedance state is recognized by its logical strength


check this out


**broken link removed**
 

there no way high Z in VHDL for syntizable model
 

hello,

Iouri is right u cannot synthesize high impedance. I was telling u at coding view.

Thanks
Viswanadh
 

Hi friends,

The high Z is added in IEEE.std_logic_1164

Do check these links.

h**p://www.vhdl-online.de/tutorial/englisch/t_71.htm#pgfId-1017643

www.cs.du.edu/~cag/courses/ENGR/ence3830/VHDL/Lectures/VHDL.PPT

FYI, the slide is shown below...

Defined in IEEE package called STD_LOGIC_1164 (“standard logic”)
Contains 9-valued STD_LOGIC type for simulation and synthesis
‘U’= uninitialized
‘X’= forcing unknown state
‘0’= forcing 0 level (logic zero)
‘1’= forcing 1 level (logic one)
‘Z’= high impedance
‘W’= weak state, level unknown
‘L’= weak 0
‘H’= weak 1
‘-’= don’t care
STD_LOGIC initializes to unknown
 

hi friends

thank for your reply
 

1. In VHDL level for simulation, You can write VHDL for compare input as 'Z'.
2. Hi-Z is not mean for synthesis. 'Z' is for assign to bidirectional pin.
3. For hardware FPGA is not design to sense Hi-Z state. So you cannot implement to FPGA.
 

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