Compare latch based and register based design

latch based design

What differences they have? What factors determine certain kind of design?Such as area ,speed ,power, and so on. What else?

latch vs register

In terms of speed latch design will always be faster and in general will be using fewer components so lesser area , register design on the other hand will be more robust,stable and less sensitive to noise.
There's a similar thread 'Moore vs Mealy design' in the same forum having similar discussion.

Regards
tronix

latch register

to tronix:

There's a similar thread 'Moore vs Mealy design' in the same forum hvn similar discussion


I don't think there is any co-relation between latch based design and register based design with STATE MACHINES what kind of similarity they have?????

latch based register design

aniketd said:

to tronix:

There's a similar thread 'Moore vs Mealy design' in the same forum hvn similar discussion


I don't think there is any co-relation between latch based design and register based design with STATE MACHINES what kind of similarity they have?????

Click to expand...

Ya sure both r State machines but the similarity is that a Moore Design is a complete synchronous Design possessing advantages and disadvantages of a synchronous Design(immunity to noise,slower speed) , A mealy design on the other hand though synchronous has the attributes of asynchronous design.

latch based designs

**broken link removed**
EE Times (07/17/2006 8:00)
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Using pulsed latch instead of flip-flop reduces the dynamic power of the clock network, which can consume half of a chip's dynamic power. Real designs have shown approximately a 20 percent reduction in dynamic power using this methodology.

Pulsed latch concept
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A latch can capture data during the sensitive time determined by the width of clock waveform. If the pulse clock waveform triggers a latch, the latch is synchronized with the clock similarly to edge-triggered flip-flop because the rising and falling edges of the pulse clock are almost identical in terms of timing.

The pulsed latch requires pulse generators that generate pulse clock waveforms with a source clock.


Designing with pulsed latches
====================
- Pulsed latch replacement and pulse generator insertion
- Skew and slew control of the clock tree
- Timing analysis and optimization
- Power analysis
- Pulse latch design rule checking


Power analysis
==========
Power analysis must distinguish the pulsed latches and normal flip flops and apply power values appropriately. Moreover, there is additional power consumed in pulse generators and delay cells. These power numbers must be considered during power analysis for comprehensive power savings.


References
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[1] P. Zuchowski, "Design Strategies for Low Power ASICs," IBM Technology Group New England Design Forum, June 18, 2003

[2] Tetsuya Yamada, et.al, "Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core", IEICE Transactions on Electronics 2006 E89-C(3), Pp 287-294

register latch

Well latch based designs are not synthesizable. They have race arounf problems thats why we prefer register based designs but naturally latch based designs are more speedy and occupy less area.