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Hi friends ,
Let me know if latches are aviable in scan chain . what tool will do?
whether it include it on scan chain or by-pass that latch.
Assumption is latch is placed in between to 2 flops. what tool will do?
if it is avoiding latch , why?
Hi ...
@ Arvind
Latches can not be included in scan chains that is the major reason (besides timing) for avoiding latchs in design (if u r not doing a latch based design). Without strict requirement anything that can be done with a latch can be done in a flop based design.
@Alerta
If u r talking abt asyn reset etc signals for flops they can be included in scan chains if these signals are controllable (not internally genrated or by including extra MUX before the signal.)
You must understand some basic concepts of DFT before putting your hands into it. If not, you keep asking questions like these...
Observability and Controllability are the basic concepts a DFT engineer should aware of... try reading something about it.
By making that async signal controllable, you are making it easy to drive any desired value on to that signal during testing. With this in place any tool can generate patterns to test the logic easily.
Define ur scan architecture, define the scan clocks, scanins scanouts,
scan control pins, use ny scan insertio tool, repair if u have any dft rule violations and then insert scan, then do post scan checking, generate patterns to detect faults, generate teser programs from them, Thats all
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