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Analysis of timing due to Clock gating cell insertion

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eda_boy

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Hi,
How to do analysis for different types of clock gating cells?
That is, I want to figure out the changes in timing due ot insertion of clock gaing cells to a flop? Is any reference available to this topic? I want mathematical analysis if possible.
Kinjal
 

please use command set_clock_gating_check, then use pt/dc to do timing check
 

PT manual has clear cut explanation of same.
 

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