Idea for introdcuing internal zero in LDO's frequency response

hello

I need a circuit which will introduce an internal zero in LDO's frequency response. I will also use an external capacitor but i could use lower esr then.

I have found one solution, but it makes problems for me. It's presented in

A robust frequency compensation scheme for LDO regulators
Chava, C.K. Silva-Martinez, J.
Analog & Mixed Signal Center, Texas A&M Univ., College Station, TX, USA

Current IB should be very low (max. 0.5uA) to not affect LDO's output voltage.
But the pole which this ciurcuit introduces is gm1/C1. Low IB means low gm1 and low frequency pole, so the compensation doesn't work.

I need something to increase gm without increasing IB current.
In the b) picture authors presented solution which should help.

Unfortunately in my design i use low vdd (1.3V) and vout equals to 0.8 so the input pair won't work properly.

How can i increase gm1 transconductance and increase input's resistance?

regards

Re: LDO internal zero

Hi, jutek:
The simplest way to add a zero in the LDO is series connect a resistor and a capacitor, then append it at the inner node, for instance at the output of opamp.
The resistor can be implemented by mos transistor which controlled by PMOS's gate voltage.
Another way you can add a feedforeard signal path to created a zero to compensated the loop.
Best wishes!!

LDO internal zero

can you upload IEEE paper
robust frequency compensation scheme for LDO regulators

or
A capacitor-free cmos low-dropout regulator with damping-factor ..

or
Single Miller Capacitor Frequency Compensation Technique for Low ...

by the way , you make LDO by BJT or CMOS process

Added after 2 minutes:

find

DMOS delivers dramatic performance gains to LDO regulators

**broken link removed**

LDO internal zero

connect a resistor to the bypass capacitor

Re: LDO internal zero

I have seen this paper before.the goal of this circuit is to increase the effective cap of C1(in the picture),the theory of the zero introduce is just as byellow said:"connect a resistor to the bypass capacitor ". in fact, you can push the pole to 5MHZ just as the author said ( I have done this) by optimize the size of current mirror and current bias transistors.The current mirror you can use cascode structure, but instead of using cascode of the IB bias mos as the paper descibed,you just use one nmos biased by the bias voltage.
For 1.3 VDD I think it is not easy, you can try to get rid of the source follower, but it may not work. I'v done this circuit with VDD=2.4V Vth=1V.

Re: LDO internal zero

Isnt the op-amp in the schematic you've presented connected as a positive feedback instead of negative one?