Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

using VHDL (if …elsif …elsif…else sentence ) meet problem

Status
Not open for further replies.
M

Matrix_YL

Advanced Member level 4
Joined
Aug 19, 2005
Messages
108
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,298
Activity points
2,272
HI all

I meet a weird thing in my design when I want to implement a state machine by use ( if …elsif…elsif…else)

Code: 
when  Waiting =>  
          if     RNW='1' then
              state_next<=Receive;
          elsif  Finish = '1' then 
              state_next<=Finish;
          elsif   Failure<='1' then
	        state_next<=Failure;
          else 
	        state_next<=Waiting;
          end if;
when RNW=1 ModelSim show that logic works fine then state_next will be Recieve. but when RNW=0 the logic will take no account of Finish Failure value and state_next will be Failure.for example Failure =0 and Finish =1 ModelSim will show the state_next will be Failure
now I wondered use if …elsif…elsif…else sentence will meet some problem .
Can you tell me why this would be happen ? any suggestion to substitute this my problem code .
thx in advance
 

Re: using VHDL (if …elsif …elsif…else sentence ) meet probl

"waitig、"finish"、"failure"、"receive" are states of the finite state machine,but why do you use some of them as the infering condition in the program,it may well be some problems here. as i see, in the diagram of the machine, the condition "finish" is just a signal or global variable rather than infering condition,it is not the same matter.it is my idea,maybe it is also wrong, but it is hoped that it will give you an idea to correct it.
 

in the if else statement, it also sometimes problem for the complier when two or more conditions are tru, you might want to think again
 

Re: using VHDL (if …elsif …elsif…else sentence ) meet probl

when Waiting =>
if RNW='1' then
state_next<=Receive;
elsif Finish = '1' then
state_next<=Finish;
elsif Failure<='1' then
state_next<=Failure;
else
state_next<=Waiting;
end if;

i guess this should be Failure='1' only
maybe this caused a problem
 

    M

    Matrix_YL

    Points: 2
    Helpful Answer Positive Rating
Re: using VHDL (if …elsif …elsif…else sentence ) meet probl

Code: 
when  Waiting =>  
          if     RNW='1' then 
              state_next<=Receive; 
          elsif  Finish = '1' then 
              state_next<=Finish; 
--          elsif   Failure<='1' then 
--           state_next<=Failure; 
          else 
           state_next<=Waiting; 
          end if;

if I comment two sentence above, if …elsif…else will be work fine but fail to go to state_next of Failure .

Can anyone tell me why if …elsif…elsif …else will make mistake however if …elsif…else will not ? how can I solve my problem ?

thx in advance
 

Re: using VHDL (if …elsif …elsif…else sentence ) meet probl

First you need to use the correct condition.

Please note that you are testing if Failure is less than or equal to '1', which is always true. Your state machine will never be in the Waiting state for more than one cycle.
 

    M

    Matrix_YL

    Points: 2
    Helpful Answer Positive Rating
Re: using VHDL (if …elsif …elsif…else sentence ) meet probl

tkbits said:
First you need to use the correct condition.

Please note that you are testing if Failure is less than or equal to '1', which is always true. Your state machine will never be in the Waiting state for more than one cycle.
Click to expand...

Why ? Can you make it more clear ?What should I do ? or give me some examples pls? how did I write my code to implement what I want ?

thx in advance
 

to Matrix_XL:
what should happen when ALL thre conditions are true?
 

Re: using VHDL (if &#8230;elsif &#8230;elsif&#82

Matrix_YL said:
Code: 
when  Waiting =>  
          if     RNW='1' then 
              state_next<=Receive; 
          elsif  Finish = '1' then 
              state_next<=Finish; 
--          elsif   Failure<='1' then 
--           state_next<=Failure; 
          else 
           state_next<=Waiting; 
          end if;

if I comment two sentence above, if …elsif…else will be work fine but fail to go to state_next of Failure .

Can anyone tell me why if …elsif…elsif …else will make mistake however if …elsif…else will not ? how can I solve my problem ?

thx in advance
Click to expand...
Just correct your code in this manner -
Code: 
when  Waiting =>  
          if     RNW='1' then 
              state_next<=Receive; 
          elsif  Finish = '1' then 
              state_next<=Finish; 
          elsif   Failure = '1' then -- but NOT:  elsif   Failure <= '1' then
           state_next<=Failure; 
          else 
           state_next<=Waiting; 
          end if;

salma ali bakr has already point you to this mistake.

Added after 3 minutes:

tkbits said:
First you need to use the correct condition.

Please note that you are testing if Failure is less than or equal to '1', which is always true. Your state machine will never be in the Waiting state for more than one cycle.
Click to expand...
<= - is not "less or equal" operator. It is a signal assignment operator in VHDL.

Added after 5 minutes:

Iouri said:
to Matrix_XL:
what should happen when ALL thre conditions are true?
Click to expand...
When all conditions are TRUE, only first will be processed, because if/elsif/else construction always present a priority structure.
 

    M

    Matrix_YL

    Points: 2
    Helpful Answer Positive Rating
Hi all

I knew what's wrong with my FSM but I don't know how to solve it. Anyone can give me correct code to solve my problem.

thx in advance
 

Re: using VHDL (if &#8230;elsif &#8230;elsif&#82

maksya said:
<= - is not "less or equal" operator. It is a signal assignment operator in VHDL.
Click to expand...

You cannot embed an assignment within an expression. In the context of an expression, <= is "less or equal".

salma ali bakr said:
i guess this should be Failure='1' only
maybe this caused a problem
Click to expand...
 

Hi all

Thank you all for your patience !I haven't notice exist
Code: 
Failure <='1'
in my design . It's my mistakes ! Maybe something make me can't concentrate on my design !
now I am clear !!
 

Re: using VHDL (if …elsif …elsif…else sentence ) meet probl

u dont use if..elsif.....

use case thats better
because

if..elsif.. leads to prirority.... first case is considered first...


use case statement.. then no pripority comes...


Regards
Shankar
 

Re: using VHDL (if …elsif …elsif…else sentence ) meet probl

seeeee matrix...i was the first one to tell u about ur tiny mistake....
thanks for the points of the HELPED ME button u pushed...

take care,
Salma:D
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top