how to calculate the gain of this circuit?

• May 15, 2006

• #1

wjxcom

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Hi, all: please look at this circuit which can be found in the book writed by Gray.
I find this circuit in the book "CMOS Circuit Design, Layout, and Simulation" writed by R.Jacob Baker too. in this book, Baker said the gain of this circuit is -gm6×(r04||r05), this value can be found in the equation 25-2 in the book writed by Baker.

Is this value is right? and why? and how to confirm the samll signal equivalent circuit?

 

• May 15, 2006

• #2

vsgiri

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Hi wjxcom!

I'm no expert in analog design but since no one else has replied I thought I might give it a try!
My reasoning goes like this.
M3 is a stiff current source sending a constant current through m4 m5 m6. This establishes a constant voltage drop in m4 and m5 (diode connected). So any small signal input gets absorbed across m6 and m3. So the gate to gate voltage b/w m1 and m2 remains fairly constant. The gain in my opinion should be close to 0.
Correct me if I'm wrong!

Giri

 

• May 15, 2006

• #3

Davood Amerion

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I think its gain must be -gM6 * roM3
because M4, M5 and M1, M2 make voltage follower (with gain of unity).

Regards,
Davood.

 

• May 15, 2006

• #4

rfsystem

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The gain of M3 and M6 is

g6*(rds3||rds6)

The output stage have a gain

(g1+g2)*RL/(1+(g1+g2)*RL)

 

• May 15, 2006

• #5

P

pthoppay

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Hi,

I feel the gain of the circuit is can be divided into 2 stages,

1) From M6 to M5 which is,

gm6/(gm5+g06)

2)From M2 to outpu, which is a source follower in this case.

gm2/(gm2+1/RL+go2+go1)

Multiplying these two will give the effective gain.

the other transistor are for biasing.

Prakash.

 

• May 16, 2006

• #6

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Hi rfsystem and pthoppay, I have 2 questions:

1. what is the output of the first stage
2.what is the input and what is the output of the output stage?

 

• May 16, 2006

• #7

Davood Amerion

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sorry i forgot to add roM6 to output gain:
its gain is -gM6 * (roM3||roM6)
ro as rfsystem said is rds
M4 and M5 make voltage shifter.
output of first stage can be drain of M6 or M3.

 

• May 16, 2006

• #8

R

rock_zhu

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I agree vsgiri's opinion. the gain is 0

 

• May 16, 2006

• #9

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the gain is 0? if its gain is zero, can this circuit be useful?

 

• May 16, 2006

• #10

E

eldo

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I think rfsystem is right, the gain is: gm6*(ro3\\ro6)

 

• May 17, 2006

• #11

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HI, rfsystem and eldo: can you explain it detailed?

 

• May 18, 2006

• #12

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Hi rfsystem: I have 2 questions:

1. what is the output port of the first stage
2.what is the input port of the output stage?

 

• May 18, 2006

• #13

rfsystem

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Exact definition of the separation is important to know only for behaviour modelling. So the input of the first stage is G(M6). The input quantity is voltage. The output of the first stage are two voltages at G(M4) and G(M5). Both are tracking but the difference set the bias of the output stage.

 

• May 18, 2006

• #14

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HI, rfsystem:do you mean that the first stage hve two output port? if so, I do not know how to calculate the output resistance of the first stage, because there will be too output resistance of the first stage, so I do not know how to calculate the gain of the first stage.

 

• May 18, 2006

• #15

S

shothand

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please refer to ghml for solution.

 

• May 18, 2006

• #16

T

tyassin

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Hi

I have been following this thread...but I am a litte confused.

The equation in Bakers book stats the same result given by rfsystem and not -gm6×(r04||r05).

There is also some approximations in the result: -gm6*(ro3\\ro6).

Regards

 

• May 19, 2006

• #17

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Hi, shothand: what is "ghml"?

 

• May 19, 2006

• #18

rfsystem

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I have made a small simplification and did not state the sign of the first stage gain

g6*(rds3||rds6)

It should be negative

-g6*(rds3||rds6)

So increasing the gate voltage of M6 related to gnd decrease the two output voltages for the second stage.

The gain of the second stage is positive.

The output resistance of the first stage is (rds3||rds6). But because the input resistance to the second stage in infinite there is no DC effect.

 

• May 19, 2006

• #19

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Hi rfsystem: I am sorry to disturb you again, but I do not know yet that why the first stage has two output port?

 

• May 19, 2006

• #20

rfsystem

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AC wise it has only one port. That is because the diodes M4&M5 set only an offset voltage for biasing the output stage.

For AC signal flow analysis it is only one port.