problem in setting input/output delay in PrimeTime

Hi,
In my current design, I have a problem in setting input/output delay in PT for my LVDS & SERDES, please help me
1. Please see the following picture
``````+-----+````````````+-------------+
POS`x-|`````|````````````|`````````|-------------->clk
``````|LVDS`|------------------|``SERDES```|
NEG`x-|`PAD`|````````````|`````````|-------------->data
``````+-----+````````````+-------------+

- How can I set_input_delay for POS & NEG pins of LVDS PAD?
- How can I control the timing from LVDS PAD to SERDES?
(The set_output_delay has the same problem)

2.
``````+-----+`````````````
POS`x-|`````|`````````````
``````|LVDS`|----------->`clk
NEG`x-|`PAD`|``````````````
``````+-----+``````````````

``````+-----+`````````````
POS`x-|`````|`````````````
``````|LVDS`|----------->`data
NEG`x-|`PAD`|``````````````
``````+-----+``````````````

- How can I create clock for (clk POS NEG ) and set_input_delay for (data POS & NEG) pins of LVDS PAD?

(The output has the same problem)

If you have experienced this, please help me. Thank you!