Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to write the below verilog code in vhdl

Status
Not open for further replies.
b <= a(1);

IMHO :))

P.S. If b is STD_LOGIC and a - STD_LOGIC_VECTOR !!!
 

b is std_logic_vector
for example
a=4
then
b=1111
 

I don't know much VHDL, but in Verilog I think b=a{1'b1}; is a syntax error.
Maybe you mean b={a{1'b1}}; but that's an error too if the repetition multiplier a is not a constant.
 

sorry, a is constan defined with 'define
 

for I in 0 to a-1 loop
b(I) <= '1';
end loop;

P.S. a is CONSTANT !!!
 

    T

    tarkyss

    Points: 2
    Helpful Answer Positive Rating
Or do something like this:
b <= NOT (ShiftLeft("1111111111111111", a)) ;
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top