SDRAM routing with FPGA

I am trying to route 2 Micron 256 Mbit (16-bit data) ICs to an FPGA. It's a Quad flatpack device, so I have 2 banks devoted for SDRAM (there are no shared signals to keep it simple). The top side of the FPGA is for module 1, and the bottom side for module 2. I have 3 questions (this is for a 4-layer board, no controlled impedance):

1) Should I place the SDRAM IC with it's long axis parallel to the FPGA pins, or should I 'stand up' the IC with it's long axis perpendicular to the FPGA pins. The first method, I can achieve shorter trace lengths for the side of the SDRAM closer to the FPGA, but I can't equalize the net lengths of the side further away from the FPGA.

If I stand up the IC, I can 'probably' achieve equal net lengths, but the average length will be longer.

Which method do you think is better?

2) How are the SDRAMs clocked?? Just through any pin on the FPGA? I have 2 PLLs on the FPGA, so I want to know if I should use a special pin for the clock on the SDRAM. This could severely restrict my placement of the SDRAM ICs.

3) For the power plane, should the whole portion under the FPGA be the core voltage, or just a 'ring' under the pins. I would think the whole portion since everything inside runs at 1.8V...

Thanks a lot!

Hi
First place the SDRAM device symmetrically and place them in center of the FPGA bank approx equal distance.

1. I clock is star routed or daisy chain ? depending on the clock topology pin assignment of other signals to be decided.

Hey - I don't understand your post too well. Should I place the SDRAM in parallel with the FPGA bank, or perpendicular?

Th eclock will be coming from the FPGA; all signals are point to point.

Hi
SDRAM should be placed parallel with th FPGA BANK

Thank you This means that the signal nets will not be equal in length though, so it that a problem?

Also, I am using a PLL out pin to a TI Clock buffer, which will then fan out to both SDRAMs.. the distance is about 1.5". Is this ok?