A
andonie12
Guest
You have three input signals and one output signal.
clk : in std_logic;
srl_data : in std_logic;
srl_data_enable : in std_logic;
prl_data : in std_logic_vector(15 downto 0);
The customer request:
1) He wants to take the serial data "srl_data" and converted to Parallel data "prl_data" but they might send you the "srl_data" and the "srl_data_enable" signals apart from each other by ± 16 bits.
The question is how do we position both the "srl_data" with the "srl_data_enable" so we can convert the "srl_data" to "prl_data"
clk : in std_logic;
srl_data : in std_logic;
srl_data_enable : in std_logic;
prl_data : in std_logic_vector(15 downto 0);
The customer request:
1) He wants to take the serial data "srl_data" and converted to Parallel data "prl_data" but they might send you the "srl_data" and the "srl_data_enable" signals apart from each other by ± 16 bits.
The question is how do we position both the "srl_data" with the "srl_data_enable" so we can convert the "srl_data" to "prl_data"