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Dear friend you have to choice suitable W/L transistor.
That is should symmetric waveform output voltage nod.
This more knowledge you see the follow:
1-. Hegazi, J. Rael, A. Abidi “The designer’s guide to high-purity oscillator”
2-A. Hajimiri, T. H. Lee, “A General Theory of Phase Noise in Electrical Oscillators” J. Solid-State Circuits, vol. 33, No. 2, Feb.1998
read more paper writen by P andreani ,Hajimiri and Abidi,
you can find the different ratio shown in different technology
and they have compared the phase noise in different structure
and there are some methods toe reduce phase noise due to low frequency noise up conversion
if you use vco in an pll, the pll's loop bandwidth will reject your 1/f noise upconverted phase noise. so it could be easy for pll phase noise performance if your pll's loop bw is a little bit higher to reject vco's low freq noise.
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