Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Performance degradation for low power input to GSM type PA?

Status
Not open for further replies.

Wilson_yu_chen

Advanced Member level 4
Joined
Jan 27, 2005
Messages
116
Helped
7
Reputation
14
Reaction score
0
Trophy points
1,296
Activity points
1,196
Hi Professionals,

Any body know the performance risk for power input lower or equal to lowest Pin in GSM PA datasheet ??

I thought power contour may change, like Pout saturation would be lower, and effeciency lower at max PCL.
Any others? like linearity performance - harmonics larger and little higher noise level.

Ususally 3 stages PA has first stage working in linear region, and last two for power gain stages. For lower input power to first stage, because of fixed gain,
2nd and 3rd stage would be driven more harder to maintain same Pout. That's why
I thought some performances will get degradation.

Any one can give me recommendation or correction ??

Thanks
 

Re: Performance degradation for low power input to GSM type

Hi,

If it is below spec, harmonics may not be much affected. But higher noise in rx is expected. I suppose you realise that most PA the keep the bias point
constant, the gain the first stage is kept high and the overall noise power is not increased when decreasing output power, as accorded to Friis equation.
I suppose operating at lower Pin would result in the PA control not in regulation as well.

Hope it helps.
 


Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top