ninja
Newbie level 4
vhdl clock divider
hai friends
i am a beginner in ASIC. In VHDL i was able to design divide by 3 or divide by 5 circuits using FSM.is it possible to get an 2/3 divider circuit ??. actually the problem is to get 33.33 MHZ from an 50 MHZ source.
kindly suggest me some technique to achieve it.
take care
bye
hai friends
i am a beginner in ASIC. In VHDL i was able to design divide by 3 or divide by 5 circuits using FSM.is it possible to get an 2/3 divider circuit ??. actually the problem is to get 33.33 MHZ from an 50 MHZ source.
kindly suggest me some technique to achieve it.
take care
bye