Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

About the gate resistance of a MOSFET

Status
Not open for further replies.
V

v_naren

Newbie level 4
Joined
Jun 16, 2005
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,337
TSMC 0.18um RFCMOS in Cadence SpectreRF

in order to find the gate resistance of a MOSFET, I try to read the gate resistance from the Smith chart for S11.
I fixed the channel length to 0.18um, and fixed number of fingers to be 64.
Then I change the value of width per finger. ( the MOSFET is properly biased and the measure frequency is 2.5GHz)

According to my knowledge, the gate resistance increases with the width per finger, however, the simulator tells me it decreases from arround 14Ohm @ 1.5um per finger to 11 Ohm@8um per finger.

anyone could kindly tell me why?
Thank you in advance!
 

is it due to the NQS effect? and the total resistance u seen is not the physical resistance alone?

I also have this doubt and wish some one could give the right answer

best regards
 

    V

    v_naren

    Points: 2
    Helpful Answer Positive Rating
i think the NQS effect can be neglected under 5GHz

the gate resistance depends heavly on the layout of the fingers and the conncetion between them

khouly
 

Anyone has any source to study RF layout??
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top