nemolee
Full Member level 3
Dear Sir,
This example describes an 8-bit signed multiplier with registered I/O in Verilog HDL. Synthesis tools detect multiplier designs in HDL code and infer lpm_mult megafunction.
I hope it is useful for you.
Best Regards
This example describes an 8-bit signed multiplier with registered I/O in Verilog HDL. Synthesis tools detect multiplier designs in HDL code and infer lpm_mult megafunction.
I hope it is useful for you.
Best Regards