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How can I drive a weak zero in Verilog?

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vivek

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hi
how can i drive a weak zero in verilog? In VHDL it can be easily done using std_logic. Also how will be this weak zero be realised in real circuit?
 

verilog tri0

Give here ur VHDL example for weak zero. I will write equivalent verilog for that!
 

verilog syntax weak

hi
in VHDL weak zero is one of the values which can be taken up by the std_logic data type. in verilog no such data type is there. then how can we model
weak zero?
 

verilog weak 0

In VHDL for weak 0 we have 'H' whoes equivalent in Verilog is tri0
 

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    vivek

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weak 0 in verilog

weak zero will be realized by weak driver,

for example, in TSMC libs, X4 strongest driver,

X1, X2, X3 moderate driver.

XL weakest driver.



vivek said:
hi
how can i drive a weak zero in verilog? In VHDL it can be easily done using std_logic. Also how will be this weak zero be realised in real circuit?
Click to expand...
 

weak pulldown in verilog

Hi, power-twq

I think that you maybe make a mistake. The lib of X1, X2, X3 ... are only for drive ability.

In each process lib, there are some pad for weak output, such as pull-up pads and pull-down pads.

You can request those datasheet from TSMC or SIMC etc.

Good Luck
 

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