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Problem in bidirectional port

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syedahmar

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hello everybody!!!
i am facing a small problem which i hope someone would solve..
i am designing a memory module which have 4 FIFOs. There in verilog code , i have an inout port DATA[31:0] and a 32 bit register data_bus.
Now during simulation, i want that when my signal rd_en is high, the contents of data_bus should be written to the inout port DATA. I have checked in simulation ,the data is there in data_bus but it doesnt write it to DATA.
my code is something like this....
assign DATA=(rd_en)?data_bus:32'bz;

During simulation, even when the rd_en signal is active, the data in DATA is the one which i had entered while rd_en was low....
Help plzzzz
 

Can you post ur complete code here? Problem seems to be some where else
tham in the statement
assign DATA=(rd_en)?data_bus:32'bz;
 

syedahmar said:
assign DATA=(rd_en)?data_bus:32'bz;
During simulation, even when the rd_en signal is active, the data in DATA is the one which i had entered while rd_en was low....
Help plzzzz
Click to expand...
What is data_bus in your design? Is it a wire, trigger or latch?
I believe you are using rd_en somewhere else in your circuits and it might cause that delay.
 

module top(clk,
sinit,
din,
wr_en,
dout,
full,
empty,
DATA,
addr_en,
rd_sel,
readout_en,
count_chk,
addr_in);

input clk,sinit,readout_en,addr_en;
input [31:0] din;
input [3:0] wr_en;
// just for checkin
output [1:0] rd_sel;
//////////////////
input [1:0] addr_in;
inout [31:0] DATA;
output [31:0] dout;
reg [31:0] dout;
output [3:0] empty,full;
wire [39:0] data_count;
wire [3:0] rd_en;
wire [31:0] dout1,dout2,dout3,dout4;
output [9:0] count_chk;
makeme block1(.clk(clk),.sinit(sinit),.din(din),
.wr_en(wr_en[0]),.rd_en(rd_en[0]),.dout(dout1),
.full(full[0]),.empty(empty[0]),
.data_count(data_count[9:0]));
makeme block2(.clk(clk),.sinit(sinit),.din(din),
.wr_en(wr_en[1]),.rd_en(rd_en[1]),.dout(dout2),
.full(full[1]),.empty(empty[1]),
.data_count(data_count[19:10]));
makeme block3(.clk(clk),.sinit(sinit),.din(din),
.wr_en(wr_en[2]),.rd_en(rd_en[2]),.dout(dout3),
.full(full[2]),.empty(empty[2]),
.data_count(data_count[29:20]));
makeme block4(.clk(clk),.sinit(sinit),.din(din),
.wr_en(wr_en[3]),.rd_en(rd_en[3]),.dout(dout4),
.full(full[3]),.empty(empty[3]),
.data_count(data_count[39:30]));
assign count_chk=data_count[29:20];
reg [31:0] data_bus;
//assign DATA[1:0]=(addr_en)?addr_in:((readout_en)?2'b00:data_bus[1:0]);
assign DATA[1:0]=(addr_en)?addr_in:data_bus[1:0];
//assign DATA[1:0]=(addr_en)?2'bz:data_bus[1:0];
assign DATA[31:2]=readout_en?30'b0:data_bus[31:2];
//assign DATA[31:2]=addr_en?30'b0:32'bz;
//assign DATA=((addr_en==1'b0)&(readout_en==1'b0))?data_bus:32'bz;
//assign DATA=readout_en?32'bz:32'bz;
//assign DATA=data_bus;
reg [1:0] rd_sel;
always@(posedge clk)
begin
if(addr_en)
rd_sel<=DATA[1:0];
end
assign rd_en=(readout_en)?(rd_sel[1]?(rd_sel[0]?4'b1000:4'b0100):(rd_sel[0]?4'b0010:4'b0001)):4'b0000;
//assign rd_en=(readout_en)?(rd_sel[1]?(rd_sel[0]?((data_count[9:0]>10'b0000110010)? 4'b1000:4'b0000):4'b0100):(rd_sel[0]?4'b0010:4'b0001)):4'b0000;
wire [31:0] mux_out;
assign mux_out=rd_sel[1]?(rd_sel[0]?dout4:dout3):(rd_sel[0]?dout2:dout1);
always@(negedge clk)
begin
data_bus<=mux_out;
dout<=DATA;
end

endmodule
////////////////////////////////////////////////////////////////////
The above is my complete code.....
 

At a glance look on your code I can tell you that data_bus signal is not controlled by rd_en at all.
And the second remark is about using of both edges of clock. I think you should avoid that, because it will cause decreasing Fmax of your design.
 

Actually i have used data_bus as a 32 bit register and rd_enable is not supposed to control it either. My objective is that the contents stored in data_bus should be written to dout register when rd_enable gets low....
this is where i am facing a problem...
helpp....
 

You should use if statement in always construction. It will be a trigger with "enable" input.
always@(negedge clk)
begin
if (!rd_en) dout <= data_bus;
end

If you need a latch, you have to use
always@(!rd_en) dout = data_bus;
It is level-sensitive and transparent at low level of rd_en.
 

Here I have tried to correct ur code! You were using both rising and falling
clk edges I changed it to posedge only! This code will at least take in correct direction!
Hope this helps you!


Code: 
module top(clk,
           sinit,
           din,
           wr_en,
           dout,
           full,
           empty,
           DATA,
           addr_en,
           rd_sel,
           readout_en,
           count_chk,
           addr_in);
   
   input clk,sinit,readout_en,addr_en;
   input [31:0] din;
   input [3:0] wr_en;
   // just for checkin
   output [1:0] rd_sel;
   //////////////////
   input [1:0] addr_in;
   inout [31:0] DATA;
   output [31:0] dout;
   reg [31:0]  dout;
   output [3:0] empty,full;
   wire [39:0] data_count;
   wire [3:0]  rd_en;
   wire [31:0] dout1,dout2,dout3,dout4;
   output [9:0] count_chk;

   reg [31:0]  DATA_reg;
   
   assign      DATA = DATA_reg;
   
   makeme block1(.clk(clk),.sinit(sinit),.din(din),
                 .wr_en(wr_en[0]),.rd_en(rd_en[0]),.dout(dout1),
                 .full(full[0]),.empty(empty[0]),
                 .data_count(data_count[9:0]));
   makeme block2(.clk(clk),.sinit(sinit),.din(din),
                 .wr_en(wr_en[1]),.rd_en(rd_en[1]),.dout(dout2),
                 .full(full[1]),.empty(empty[1]),
                 .data_count(data_count[19:10]));
   makeme block3(.clk(clk),.sinit(sinit),.din(din),
                 .wr_en(wr_en[2]),.rd_en(rd_en[2]),.dout(dout3),
                 .full(full[2]),.empty(empty[2]),
                 .data_count(data_count[29:20]));
   makeme block4(.clk(clk),.sinit(sinit),.din(din),
                 .wr_en(wr_en[3]),.rd_en(rd_en[3]),.dout(dout4),
                 .full(full[3]),.empty(empty[3]),
                 .data_count(data_count[39:30]));
   assign      count_chk = data_count[29:20];
   reg [31:0]  data_bus;

/* -----\/----- EXCLUDED -----\/-----
   assign      DATA[1:0]=(addr_en)?addr_in:data_bus[1:0];
   assign      DATA[31:2]=readout_en?30'b0:data_bus[31:2];
 -----/\----- EXCLUDED -----/\----- */
   
   always@(/*AS*/addr_en or addr_in or data_bus or readout_en) begin
      DATA_reg = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
      if (readout_en)
        if (addr_en)
          DATA_reg = {30'b0,addr_in};
        else
          DATA_reg = data_bus;
   end
   
   reg [1:0]   rd_sel;
   always@(posedge clk)
     begin
        if(addr_en)
          rd_sel<=DATA[1:0];
     end

   assign rd_en=(readout_en)?(rd_sel[1]?(rd_sel[0]?4'b1000:4'b0100):(rd_sel[0]?4'b0010:4'b0001)):4'b0000;

   wire [31:0] mux_out;
   assign      mux_out=rd_sel[1]?(rd_sel[0]?dout4:dout3):(rd_sel[0]?dout2:dout1);

   always@(posedge clk)
     begin
        data_bus <= mux_out;
        dout <= DATA;
     end
   
endmodule
 

Ty the logic (controlling in-out port) different module and the ram or fifo's in a different module. Even i had the same problem when i was designing and then later on changed to different modules. and there is one more problem when u r forcing the data and the enabling signals while reading after writing, try with test benches it works fine.

hope this helps
 

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