Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to change verilog code to VHDL code

Status
Not open for further replies.
T

TCY02

Junior Member level 3
Joined
Mar 5, 2005
Messages
25
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,486
ramp counter vhdl

how to change verilog code to VHDL code
actually the code is like that
-----------------------------------------------------------------------

module music(clk, q);
input clk;
output q;

reg [22:0] tone;
always @(posedge clk) tone <= tone+1;

wire [6:0] ramp = (tone[22] ? tone[21:15] : ~tone[21:15]);
wire [14:0] clkdivider = {2'b01, ramp, 6'b000000};

reg [14:0] counter;
always @(posedge clk) if(counter==0) counter <= clkdivider; else counter <= counter-1;

reg q;
always @(posedge clk) if(counter==0) q <= ~q;

endmodule
-------------------------------------------------------------------------------------------
 

Use X-HDL. It offers both way conversions. But most of the times u hv to do ceratin changes. TestBenches are most hard to convert.
 

where can get this software
 

did u test this code?
whatz the intial value for the "tone" variable?
hope this will give false simulation results.

the code looks simple, we can manully convert it to vhdl
 

Here goes the translated code!
I translated manually!
Hope this helps!

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity music is
  
  port (
    clk : in  std_logic;
    q   : out std_logic);

end music;
architecture music_behave of music is
signal tone : std_logic_vector(22 downto 0) := "0000000000000000000000";
signal ramp : std_logic_vector(6 downto 0);
signal clkdivider : std_logic_vector(14 downto 0);
signal counter : std_logic_vector(14 downto 0);
begin  -- music_behave
  
  ramp <=  tone(21 downto 15) xor ((not tone(22)) & (not tone(22)) & (not tone(22))
                                 &(not tone(22)) &(not tone(22)) &(not tone(22)) &(not tone(22)));
           
  clkdivider <= "01" & ramp & "000000";
  
  process (clk)
    variable q_tmp : std_logic := '0';
  begin  -- process
    if clk'event and clk = '1' then  -- rising clock edge
      tone <= tone + '1';
      if (counter = 0) then
        counter <= clkdivider;
        q_tmp := not q_tmp;
      else
        counter <= counter - 1;
      end if;
    end if;
    q <= q_tmp;
  end process;
end music_behave;
 

oops looks like I am late, anyway, here is the translation for vhdl:
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity music is
port( clk: in std_logic;
        q: out std_logic
     );
end music;

architecture arch of music is
signal tone: std_logic_vector(22 downto 0):=(others => '0');
signal ramp: std_logic_vector(6 downto 0);
signal clkdivider: std_logic_vector(14 downto 0);
signal counter: std_logic_vector(14 downto 0);
signal temp: std_logic:='0';

begin

ramp <= tone(21 downto 15) when (tone(22) = '1') else tone(21 downto 15) xor "1111111";
clkdivider <= ("01" & ramp & "000000");

process(clk)
begin
  if rising_edge(clk) then
    if(counter = "000000000000000") then
      counter <= clkdivider;
      temp <= not temp;
    else
      counter <= counter - "000000000000001";
    end if;
  end if;
end process;
q<= temp;

end arch;
 

any other time you need to do something like this use X-hdl beeing carefull to manually optimize then the results..


maxer
 

best tool for verliog to vhdl ,vhdl to verilog is XHDL .it will transform faster and efficent manner. try this software . u will get good result.
enjoy
 

i wonder why you want chang verilog to vhdl?
i just want chang vhdl code to verilog
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top