RonC
Newbie level 1
ncmirror
Is there a way in a Cadence simulation flow (ncsim) to access a hierarchical Verilog signal from a VHDL testbench, or a hierarchical VHDL signal from a Verilog testbench? Cadence has the nc_mirror feature which replicates the hierarchical referencing capabilities of Verilog, but is there a mixed-language equivalent?
Is there a way in a Cadence simulation flow (ncsim) to access a hierarchical Verilog signal from a VHDL testbench, or a hierarchical VHDL signal from a Verilog testbench? Cadence has the nc_mirror feature which replicates the hierarchical referencing capabilities of Verilog, but is there a mixed-language equivalent?