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Multifinger Simulation en LTSpice

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lucianom

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I try to simulate in LTSpice an NMOS transistor with a 3 finger layout. That is, the Wfinal = Winitial / 3 and CSB = 2CSB / 3.
How should I simulate this in LTSpice? does the parameter "parallel devices M" already do that? or how should I use the values "source area AD" and "source perimeter SP"?
Sin título.png
thank in advance.

Luciano Martinez
 

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