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[SOLVED] Glitch Filter VHDL // Lattice document

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The Figure 2 digital filter circuit from the document shows this:
Capture.PNG
And does the following:
  • set output high if all bits in shift register are 1's
  • set output low if all bits in shift register are 0's
This basically means that the input has to be stable for n clock cycles before it's considered a valid change to a new value.

Simply translate it to an HDL

Code Verilog - [expand]
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module dfc #(
  parameter n = 5 // e.g. 100 MHz, 5 taps, 50ns filter time
) (
  input clk;
  input in;
  output reg out
);
reg [n-1:0] shift_reg;
always @(posedge clk) begin
  // shift register for input in.
  shift_reg <= {shift_reg[n-2:0], in};
  // set/reset flip-flop
  if      (&shift_reg)  out <= 1'b1;  // all one's condition on shift_reg, & is reduction AND
  else if (~|shift_reg) out <= 1'b0;  // all zero's condition on shift_reg, ~| is a reduction NOR
end
endmodule


Hardware Description Language - all I did was write in Verilog the circuit drawn in Figure 2.

BTW when I read the above code I see the circuit in Fig 2. If I see the circuit in Fig 2 I see the code I posted. To me they are the same thing described as a picture or as text.

I think that this is why so many people with heavy software backgrounds have trouble with VHDL/Verilog because they don't see the hardware schematic when reading the code. Instead they see a software program. Conversely when they get a schematic of a circuit they can translate it to VHDL/Verilog, because they can't see the schematic as code.
 
Thank you! Yes I'm still learning. It took me a long time to figure out that my problem is a glitch issue due to the "bad" design, I'm using an FPGA breakout board which has a bad routing which easily picks up noise.

https://www.edaboard.com/showthread.php?t=150553&p=648584&viewfull=1#post648584

The glitches are indeed randomly within 50ns and I figured the requirement of a filter (in this setup) is not because of speed but especially because of the bad design.
 

You'll see that above a certain noise level, the simple all-1 / all-0 logic suggested in the document isn't optimal. You better implement some kind of majority logic, as it's done in some classical UART receiver modules.
 
You'll see that above a certain noise level, the simple all-1 / all-0 logic suggested in the document isn't optimal. You better implement some kind of majority logic, as it's done in some classical UART receiver modules.

What is this some sort of 2/3 of the bits in the bit time are either 1 or 0 so the result is 1 or 0 respectively?
 
Yes, or 5-6 out of 8, or something similar. The idea is that a single glitch inside an almost stable 0 or 1 should no prevent recognition of the bit value.
 
ok everything's clear now.

I'm also implementing an I2C-slave I have used the "filtering"-way which is described in the lattice document (I'm using 3 taps), my clock is running at 12mhz.
The glitches (visible with the scope) usually come up within 1 clock cycle (within 84ns). In this case I can see the need of the 50ns filter.

I hope once I have my final PCB and do not rely on jumpwiring separate boards anymore the glitches will be gone.
 

#6 This sound like some best practices stuff.

Where did you learn this? Is there anything published on this?

I think it's important to know fixes to rubbish hardware/development prototypes.
 

Hi,

I sometimes use an up-down-counter as filter.

Clk = system_clock
EN = either 1 or a divided system clock
Dir = is the input I want to de-glitch

Thus a "1" signal makes the counter to count up
a "0" signal makes the counter to count down.

On upper limit I set the the (deglitched) output as "1", and prevent the counter from further counting up
On lower limit I set the the (deglitched) output as "0", and prevent the counter from further counting down

on a 4 bit counter you could set the lower limit to "0" and the upper limit to "15" (decimal)
Then you get a deglitch time of 15 counter_clock_cycles in both directions.
In case of a n "wrong" glitches you need 2 x n extra counts for the output to switch.

This saves flipflops especially for long deglitch times.
With n flipflops you can get a delay time of up to 2^(n-1) -1 clock cycles... in both directions.

Klaus
 

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