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To investigate Nbti on 6T SRAM

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Shimah

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Hi,
I would like to ask on how i can implement nbti model on sram circuit. I dont have any idea about it. Currently, i have been doing my research on this topic. Can anyone help me to solve this problem as soon as possible because i really need this answer.
 

Read up on the NBTI mechanism and the typical drifts (if
possible, find a foundry reliability report for the technology
of choice, for data). Then you tweak the SPICE / Spectre
model to emulate the VT shift, leakage rise, gm degradation
or whatever is shown in the test data.

Nothing need be done to the cell circuit or whatever other
bits of the RAM you care to poke at, it's device level stuff
so just swap models.

Now I have to wonder just what research you have been
doing, that this has eluded you thus far. It's not like this
is new stuff or unpublished.
 

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