[SOLVED] line regulation of voltage reference problem

I have a problem solving for a stable 0.4~.5 vref in my simulations. All transistors are saturated except for start-up.

My current reference in pmos opamp is 500nA, and 60+db gain opamp with 60* PM.

VDD = 1.2V

I already solved the value of resistors. I cant really get a stable output, some expert can help?

I have attached the temperature and VDD variation results as well as my circuit.

None of what you show, matches the problem description.
The VDD variation results you mention are not here.

I'm sorry wrong word. The first picture that is ramp then stabilizes at 1.2V. the vref is not stable as shown. If you could just identify the problem.

The supply risetime seems unrealistic unless you are
applying an estabished supply through a load switch.
A DC-DC will have risetimes in mS or longer. Starting
from zero, everything in the reference is "playing
catch-up", large signal, not a small-signal stability
problem.

First step: determine whether the overshoot and
undershoot have any actual consequences. Who in
the bigger picture is ready to do anything with the
reference, 20uS after start of supply ramp? Bueller?

Second step, add enough output filter or overcompensate
the reference feedback loop to make reference rise
monotonically.

Or, add a "RefGood" function and a switch, so ref stays
at GND until core is lit up, then attach to the output
with only a RC-like profile (no whoop-de-do). This might
be more widely useful, let the system know not to do
anything with bad inputs.