Puppet123
Full Member level 6
Hello,
I have designed a 3 stage amplifier at about 40GHz in CMOS.
I have done the layout using this methodology:
1) Layout Each Stage and then do RC extraction
-If interconnect is in DC path, ignore it
2) Connect them together using interconnect in Layout
3) I mimic the interconnect in schematic
Now some process kits, like IBM/Globalfoundries there is a TLINE component and a singlewire component.
I use the singlewire component in the schematic to see what effect the interconnect has on my design between stages in the RF path.
Or I could EM simulate all the interconnect lengths.
4) I use the TLINE component in layout for the interconnect I just simulated in the schematic.
Is this a proper methodology ?
Also, what the minimum interconnect length at a certain frequency before I have to EM simulate it ? At 30 GHz and below "can I get away with" not EM simulating the interconnect ?
Thanks.
I have designed a 3 stage amplifier at about 40GHz in CMOS.
I have done the layout using this methodology:
1) Layout Each Stage and then do RC extraction
-If interconnect is in DC path, ignore it
2) Connect them together using interconnect in Layout
3) I mimic the interconnect in schematic
Now some process kits, like IBM/Globalfoundries there is a TLINE component and a singlewire component.
I use the singlewire component in the schematic to see what effect the interconnect has on my design between stages in the RF path.
Or I could EM simulate all the interconnect lengths.
4) I use the TLINE component in layout for the interconnect I just simulated in the schematic.
Is this a proper methodology ?
Also, what the minimum interconnect length at a certain frequency before I have to EM simulate it ? At 30 GHz and below "can I get away with" not EM simulating the interconnect ?
Thanks.