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Im doing a 7-segment multiplexing code but I have an error and the bcd part is wrong

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7mod998

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im doing a 7-segment multiplexing code but i have error and bcd part is wrong


Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity sevensegment_multiplexing is
    Port ( clk50M : in  STD_LOGIC;
           an : out  STD_LOGIC_vector(3 downto 0);
           cath : out  STD_LOGIC_vector(6 downto 0);
           bcd : in  STD_LOGIC_vector(3 downto 0));
end sevensegment_multiplexing;
 
architecture Behavioral of sevensegment_multiplexing is
signal dig0,dig1,dig2,dig3:std_logic_vector(6 downto 0);
signal clk1hz,clk1k:std_logic;
begin
 
clk1k_div:process(clk50M)
           variable c: integer range 0 to 50000;
              begin 
              if(clk50M'event and clk50M='1')then
              c:=c+1;
              if(c=50000)then clk1k<='0'; c:=0;
              elsif(c=25000)then clk1k<='1';
               elsif(c<25000)then clk1k<='0';
                end if;
                end if;
                end process clk1k_div;
 
MUX_7Seg:process(clk1k)
variable S: integer range 0 to 3;
begin
if( clk1k'event and clk1k='1')then
S:=1;
Case S is
when 0=>cath<=dig0;
         an<="1110";
when 1=>cath<=dig1;
         an<="1101";
when 2=>cath<=dig2;
         an<="1011";
when 3=>cath<=dig3;
         an<="0111";    
    
end case;
end if; 
    end process MUX_7Seg    ;   
    
clk1hz_div:process(clk50M)
           variable c: integer range 0 to 50000000;
              begin 
              if (clk50M'event and clk50M='1')then
              c:=c+1;
              if(c=50000000)then clk1hZ<='0'; c:=0;
              elsif(c=25000000)then clk1hZ<='1';
               elsif(c<25000000)then clk1hZ<='0';
                end if;
                end if;
                end process clk1hz_div;
 
process(bcd)
begin
 
case bcd is
when "0000" =>
cath <= "0000001"; 
when "0001" =>
cath <= "1001111"; 
when "0010" =>
cath <= "0010010"; 
when "0011" =>
cath <= "0000110"; 
when "0100" =>
cath <= "1001100"; 
when "0101" =>
cath <= "0100100"; 
when "0110" =>
cath <= "0100000"; 
when "0111" =>
cath <= "0001111";
when "1000" =>
cath <= "0000000"; 
when "1001" =>
cath <= "0000100"; 
when others =>
cath <= "1111111"; 
end case;
end process;
 
cnt_1hz:process(clk1hZ)
variable c: integer range 0 to 50000000;
begin
if(clk1hZ'event and clk1hZ='1')then
c:=c+1;
elsif(c=50000000)then
c:=0;
clk1hZ<='0';
elsif(c=25000000)then
clk1hZ<='1';
elsif(c<25000000)then
clk1hZ<='0';
end if;
end process cnt_1hz;
                
 
end Behavioral;

 

Re: im doing a 7-segment multiplexing code but i have error and bcd part is wrong

You've posted no question here, just some code. But there are a lot of issues with your code. I'm not even sure where to begin.

First, it looks like you're trying to generate a 1KHz clock and a 1Hz clock from a 50MHz clock. That's a pretty messy way of doing it. I usually use clock enables, but if you really want to use 3 clocks, go ahead. But you should look into a better way of doing it.

But your biggest problems are:

1) S always equals one.
2) dig0, dig1, etc. never get assigned any value.
 

Re: im doing a 7-segment multiplexing code but i have error and bcd part is wrong

Another poster that doesn't know how to count from 0.

if(c=50000000)then clk1hZ<='0'; c:=0;

counts from 0 to 50000000 which is 50000001 counts

Can't believe how many people make that mistake even working engineers...that's strange we're getting over/under flows in our processing chain like there is some kind of frequency drift. It works flawlessly after a reset but always happens after a few hours of running....
 

Re: im doing a 7-segment multiplexing code but i have error and bcd part is wrong

In this case, the frequency divider counts correctly because it uses "blocking" variable assignments. But it's bad design practice in several regards:

- it's bad to use variable instead of signals for the counter due to the timing of multiple assignments in one clock cycle. (In this special case, the construct can be considered as a useful behavioral description, functional equivalent to a counter using signals, better you don't even start to write RTL code this way though)

- it's bad to use clock dividers instead of clock enables

Beside of this style points, the design doesn't work because it has been stopped somewhere on the way, as already stated by barry.

Start with defining an appropriate interface. You want to display 4 digits, but have only one bcd input. How's the display data expected to enter the unit?

As suggested a million times: Sketching a logic block diagram would surely help.
 

Re: im doing a 7-segment multiplexing code but i have error and bcd part is wrong

In this case, the frequency divider counts correctly because it uses "blocking" variable assignments. But it's bad design practice in several regards:

- it's bad to use variable instead of signals for the counter due to the timing of multiple assignments in one clock cycle. (In this special case, the construct can be considered as a useful behavioral description, functional equivalent to a counter using signals, better you don't even start to write RTL code this way though)
Oops, didn't even notice the variable used as a counter I only noticed the compares.

Here is a good reason why you don't want to use variables in a counter:
test1 - variable counter divide by 10 written like above code.

Code VHDL - [expand]
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library ieee;
    use ieee.std_logic_1164.all;
 
entity test is
port (
    clk_10m : in  std_logic;
    clk_1m  : out std_logic
);
end test;
 
architecture behave of test is
 
begin
 
  clk_div: process(clk_10m)
    variable c : integer range 0 to 10;
  begin 
    if rising_edge(clk_10m) then
      c := c + 1;
      if (c = 10) then
        clk_1m <='0';
        c := 0;
      elsif (c = 5) then
        clk_1m <= '1';
      elsif (c < 5) then
        clk_1m <= '0';
      end if;
    end if;
  end process clk_div;
 
end behave;


Elaborated RTL circuit...
var_cntr_rtl.PNG
Synthesised circuit...
var_cntr_synth.PNG
Take note of the number of cells used

test2 - signal counter divide by 10.

Code VHDL - [expand]
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library ieee;
    use ieee.std_logic_1164.all;
 
entity test2 is
port (
    clk_10m : in  std_logic;
    clk_1m  : out std_logic
);
end test2;
 
architecture behave of test2 is
  signal c : integer range 0 to 9;
 
begin
 
  clk_div: process(clk_10m)
  begin 
    if rising_edge(clk_10m) then
      if (c < 9) then
        c <= c + 1;
      else
        c <= 0;
      end if;
      if (c < 5) then
        clk_1m <= '0';
      else
        clk_1m <= '1';
      end if;
    end if;
  end process clk_div;
 
end behave;


Elaborated RTL circuit...
sig_cntr_rtl.PNG
Notice there are less layers of logic between flip-flops.
The synthesized circuit...
sig_cntr_synth.PNG

- - - Updated - - -

The take away here is that using variables for counters and other registered logic ends up with the flip-flops before a bunch of combinational logic (see first picture).

In the variable case the +1 operation occurs after the flip-flops and then feeds the compare operations. Both the counting and the compares are adding delay to the path.

In the signal case the +1 operation occurs before the flip-flops and the output of the flip-flops feed the compare operations, this reduces the logic on the output of the counter resulting in a higher Fmax.
 
Re: im doing a 7-segment multiplexing code but i have error and bcd part is wrong

I genuinely don't see the problem with using variables... -__-

Can anyone point me to a source that explains why variables are bad for counters. What about using them for FSM?
 

Re: im doing a 7-segment multiplexing code but i have error and bcd part is wrong

I genuinely don't see the problem with using variables... -__-

Can anyone point me to a source that explains why variables are bad for counters. What about using them for FSM?

Look at the elaborated RTL pictures in my post. If you can't see why the first variable version is worse than the second signal version then you should probably avoid doing any high speed digital designs (and I'm not talking about 100 MHz designs more like 500+MHz designs).
 

Re: im doing a 7-segment multiplexing code but i have error and bcd part is wrong

I genuinely don't see the problem with using variables... -__-

Can anyone point me to a source that explains why variables are bad for counters. What about using them for FSM?

There is nothing inherently wrong with using variables - the problem is when you use them without understanding the consequences on the final circuit.
Anything you can do with variables in RTL can also be done with signals, but not the other way round.

Variables are VERY useful in simulation. But thats another topic.
 

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